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| author | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-21 16:40:01 -0700 |
|---|---|---|
| committer | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-21 16:40:01 -0700 |
| commit | 4c80b12b1a96fee64bfbdd35d097d867599eee1e (patch) | |
| tree | 89e52f2a9850db98488b6078c353e6751705eaf6 /riscv/encoding.h | |
| parent | f7a7557273b050ddc50dbff09c0c4bf8505e4ac7 (diff) | |
| download | spike-4c80b12b1a96fee64bfbdd35d097d867599eee1e.zip spike-4c80b12b1a96fee64bfbdd35d097d867599eee1e.tar.gz spike-4c80b12b1a96fee64bfbdd35d097d867599eee1e.tar.bz2 | |
riscv: remove dependency on num_cores
Diffstat (limited to 'riscv/encoding.h')
| -rw-r--r-- | riscv/encoding.h | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index 60ee674..ef68c2f 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -137,9 +137,6 @@ #define IRQ_HOST 13 #define DEFAULT_RSTVEC 0x00001000 -#define DEFAULT_NMIVEC 0x00001004 -#define DEFAULT_MTVEC 0x00001010 -#define CONFIG_STRING_ADDR 0x0000100C #define EXT_IO_BASE 0x40000000 #define DRAM_BASE 0x80000000 |