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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-17 13:51:59 -0700 |
| commit | 68aeeb5500521ff52c216862f9a653b64191f3ad (patch) | |
| tree | 407230ff48f79f177a792451598d9b2b6e3d34a0 /riscv/dts.cc | |
| parent | 191634d2854dfed448fc323195f9b65c305e2d77 (diff) | |
| parent | 03be4ae6c7b8e9865083b61427ff9724c7706fcf (diff) | |
| download | spike-68aeeb5500521ff52c216862f9a653b64191f3ad.zip spike-68aeeb5500521ff52c216862f9a653b64191f3ad.tar.gz spike-68aeeb5500521ff52c216862f9a653b64191f3ad.tar.bz2 | |
Merge branch 'master' into plic_uart_v1plic_uart_v1
Diffstat (limited to 'riscv/dts.cc')
| -rw-r--r-- | riscv/dts.cc | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/riscv/dts.cc b/riscv/dts.cc index e6b810d..6a40565 100644 --- a/riscv/dts.cc +++ b/riscv/dts.cc @@ -14,6 +14,7 @@ std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz, reg_t initrd_start, reg_t initrd_end, const char* bootargs, + size_t pmpregions, std::vector<processor_t*> procs, std::vector<std::pair<reg_t, mem_t*>> mems) { @@ -58,7 +59,7 @@ std::string make_dts(size_t insns_per_rtc_tick, size_t cpu_hz, " compatible = \"riscv\";\n" " riscv,isa = \"" << procs[i]->get_isa().get_isa_string() << "\";\n" " mmu-type = \"riscv," << (procs[i]->get_isa().get_max_xlen() <= 32 ? "sv32" : "sv57") << "\";\n" - " riscv,pmpregions = <16>;\n" + " riscv,pmpregions = <" << pmpregions << ">;\n" " riscv,pmpgranularity = <4>;\n" " clock-frequency = <" << cpu_hz << ">;\n" " CPU" << i << "_intc: interrupt-controller {\n" @@ -212,7 +213,6 @@ std::string dts_compile(const std::string& dts) return dtb.str(); } - static int fdt_get_node_addr_size(void *fdt, int node, reg_t *addr, unsigned long *size, const char *field) { @@ -274,7 +274,6 @@ static int check_cpu_node(void *fdt, int cpu_offset) return 0; } - int fdt_get_offset(void *fdt, const char *field) { return fdt_path_offset(fdt, field); |