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author | Tim Newsome <tim@sifive.com> | 2016-04-24 08:54:19 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
commit | d999dfc0d41a119730ff8944d37dbee88bf99723 (patch) | |
tree | 2268c9d7d5f122fb81253d10bd05901eaff0ff62 /riscv/devices.h | |
parent | 191671a2015136c429394fd3051e4a9c1ff45352 (diff) | |
download | spike-d999dfc0d41a119730ff8944d37dbee88bf99723.zip spike-d999dfc0d41a119730ff8944d37dbee88bf99723.tar.gz spike-d999dfc0d41a119730ff8944d37dbee88bf99723.tar.bz2 |
Add debug_module bus device.
This should replace the ROM hack I implemented earlier, but for now both
exist together.
Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
Diffstat (limited to 'riscv/devices.h')
-rw-r--r-- | riscv/devices.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/riscv/devices.h b/riscv/devices.h index cb3b6d9..8378188 100644 --- a/riscv/devices.h +++ b/riscv/devices.h @@ -11,6 +11,9 @@ class abstract_device_t { public: virtual bool load(reg_t addr, size_t len, uint8_t* bytes) = 0; virtual bool store(reg_t addr, size_t len, const uint8_t* bytes) = 0; + // Return a pointer to the start of the page that addr falls in, or NULL if + // there is no IO device at that address. + virtual char* page(reg_t addr) { return NULL; } virtual ~abstract_device_t() {} }; @@ -18,6 +21,9 @@ class bus_t : public abstract_device_t { public: bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); + // Return a pointer to the start of the page that addr falls in, or NULL if + // there is no IO device at that address. + char* page(reg_t paddr); void add_device(reg_t addr, abstract_device_t* dev); private: |