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authorAndrew Waterman <andrew@sifive.com>2023-02-04 18:02:19 -0800
committerAndrew Waterman <andrew@sifive.com>2023-02-04 18:12:56 -0800
commit749b03f3b86b601dee814d4299deee3e97e0e3b7 (patch)
tree090d3f7a918598efc59f6fad86c8591e6e0efd4a /riscv/devices.h
parentb04229ee59cbe5286478b7cfa930b9995d2bdd93 (diff)
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Correctly instantiate PLIC contexts for mixed-hart targets
This commit started as an attempt to make the PLIC tolerant of discontiguous hart IDs, but it turns out it was already most of the way there: PLIC contexts can still be dense even if the hart IDs are not. Nevertheless, I wanted to avoid passing the procs vector directly to the plic_t constructor. In removing it, I realized I could also get rid of the smode parameter by querying whether each hart has S-mode. This is also more correct; previously, we were instantiating the PLIC as though all harts had S-mode, regardless of whether they actually did.
Diffstat (limited to 'riscv/devices.h')
-rw-r--r--riscv/devices.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/devices.h b/riscv/devices.h
index 53db96a..6facaa3 100644
--- a/riscv/devices.h
+++ b/riscv/devices.h
@@ -12,6 +12,7 @@
#include <utility>
class processor_t;
+class sim_t;
class bus_t : public abstract_device_t {
public:
@@ -91,7 +92,7 @@ struct plic_context_t {
class plic_t : public abstract_device_t, public abstract_interrupt_controller_t {
public:
- plic_t(std::vector<processor_t*>&, bool smode, uint32_t ndev);
+ plic_t(sim_t*, uint32_t ndev);
bool load(reg_t addr, size_t len, uint8_t* bytes);
bool store(reg_t addr, size_t len, const uint8_t* bytes);
void set_interrupt_level(uint32_t id, int lvl);