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authorTim Newsome <tim@sifive.com>2016-05-01 12:05:48 -0700
committerTim Newsome <tim@sifive.com>2016-05-23 12:12:11 -0700
commit990c6c48098e83584edf5282d119187abae04a4d (patch)
treed2ba581b281dce0c329822f98cc7c21faf868323 /riscv/devices.cc
parent57ff1b6595e485b8b002238ddbd10483bbd62fb3 (diff)
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Have Debug memory kind of working again.
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
Diffstat (limited to 'riscv/devices.cc')
-rw-r--r--riscv/devices.cc13
1 files changed, 4 insertions, 9 deletions
diff --git a/riscv/devices.cc b/riscv/devices.cc
index e6f5d7d..4e88a1d 100644
--- a/riscv/devices.cc
+++ b/riscv/devices.cc
@@ -7,9 +7,12 @@ void bus_t::add_device(reg_t addr, abstract_device_t* dev)
bool bus_t::load(reg_t addr, size_t len, uint8_t* bytes)
{
+ fprintf(stderr, "bus load(0x%lx, %ld)\n", addr, len);
auto it = devices.lower_bound(-addr);
- if (it == devices.end())
+ if (it == devices.end()) {
+ fprintf(stderr, " -> false\n");
return false;
+ }
return it->second->load(addr - -it->first, len, bytes);
}
@@ -20,11 +23,3 @@ bool bus_t::store(reg_t addr, size_t len, const uint8_t* bytes)
return false;
return it->second->store(addr - -it->first, len, bytes);
}
-
-char* bus_t::page(reg_t paddr)
-{
- auto it = devices.lower_bound(-paddr);
- if (it == devices.end())
- return NULL;
- return it->second->page(paddr);
-}