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| author | Andrew Waterman <aswaterman@gmail.com> | 2015-01-02 17:29:05 -0800 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2015-01-02 17:29:05 -0800 |
| commit | ec297672b0c9d58d1ee6c2ac976ccf28863bd3c2 (patch) | |
| tree | 3ddc58262ddca8b2f610cff9e53bf4390a989d8c /riscv/decode.h | |
| parent | 3fd738af16ef977f1aa507e2525bb4c16fff9026 (diff) | |
| download | spike-ec297672b0c9d58d1ee6c2ac976ccf28863bd3c2.zip spike-ec297672b0c9d58d1ee6c2ac976ccf28863bd3c2.tar.gz spike-ec297672b0c9d58d1ee6c2ac976ccf28863bd3c2.tar.bz2 | |
On misaligned fetch, set EPC to target, not branch itself
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index b325c59..6d1ffbe 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -155,11 +155,7 @@ private: ((x) & 0x3f) < 0x3f ? 6 : \ 8) -#define set_pc(x) \ - do { if ((x) & 3 /* For now... */) \ - throw trap_instruction_address_misaligned(x); \ - npc = sext_xprlen(x); \ - } while(0) +#define set_pc(x) (npc = sext_xprlen(x)) #define validate_csr(which, write) ({ \ unsigned my_priv = (STATE.sr & SR_S) ? 1 : 0; \ |