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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2014-12-04 23:08:01 -0800 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2014-12-04 23:08:01 -0800 |
commit | cec752d09191e96a51f5c21ed8d51e1218f804ff (patch) | |
tree | 80a611deb7791f4dbe2ac8d726f761aa13cd2374 /riscv/decode.h | |
parent | 992205c27048709b85c2655bc5ce797dd2246f75 (diff) | |
download | spike-cec752d09191e96a51f5c21ed8d51e1218f804ff.zip spike-cec752d09191e96a51f5c21ed8d51e1218f804ff.tar.gz spike-cec752d09191e96a51f5c21ed8d51e1218f804ff.tar.bz2 |
Set badvaddr on instruction page faults
This supports distinguishing the EPC (the address of the first byte of the
faulting instruction) from the address of the page fault (potentially some
bytes later).
Diffstat (limited to 'riscv/decode.h')
-rw-r--r-- | riscv/decode.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 9890514..543080d 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -155,7 +155,7 @@ private: #define set_pc(x) \ do { if ((x) & 3 /* For now... */) \ - throw trap_instruction_address_misaligned(); \ + throw trap_instruction_address_misaligned(x); \ npc = sext_xprlen(x); \ } while(0) |