diff options
author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-05-21 00:21:46 -0700 |
---|---|---|
committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-05-31 18:29:45 -0700 |
commit | bdcb5b297f9919bdd1a1b6031a3b5c469e982d14 (patch) | |
tree | a9c411e8bd1dba295217d8aa28f23b56d4f39313 /riscv/decode.h | |
parent | 292fef830dad9d6d8b868ba27cf4ddd80bf9243a (diff) | |
download | spike-bdcb5b297f9919bdd1a1b6031a3b5c469e982d14.zip spike-bdcb5b297f9919bdd1a1b6031a3b5c469e982d14.tar.gz spike-bdcb5b297f9919bdd1a1b6031a3b5c469e982d14.tar.bz2 |
New RV64C proposal
Diffstat (limited to 'riscv/decode.h')
-rw-r--r-- | riscv/decode.h | 59 |
1 files changed, 35 insertions, 24 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 4d4c447..4f57656 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -22,6 +22,9 @@ typedef uint64_t freg_t; const int NXPR = 32; const int NFPR = 32; +#define X_RA 1 +#define X_SP 2 + #define FP_RD_NE 0 #define FP_RD_0 1 #define FP_RD_DN 2 @@ -72,18 +75,22 @@ public: uint64_t csr() { return x(20, 12); } int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); } + int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); } + int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(5, 1) << 5) + (x(2, 3) << 6) + (xs(12, 1) << 9); } int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); } int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); } - int64_t rvc_lw_imm() { return (x(5, 2) << 3) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); } - int64_t rvc_ld_imm() { return (x(5, 2) << 3) + (x(10, 1) << 6) + (x(11, 1) << 7) + (x(12, 1) << 5); } - int64_t rvc_j_imm() { return (xs(2, 3) << 9) + (x(5, 2) << 3) + (x(7, 1) << 1) + (x(8, 2) << 7) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); } - int64_t rvc_b_imm() { return (x(5, 2) << 3) + (x(7, 1) << 1) + (xs(8, 2) << 7) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); } + int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); } + int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); } + int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); } + int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); } + int64_t rvc_j_imm() { return (x(3, 4) << 1) + (x(2, 1) << 5) + (xs(7, 6) << 6); } + int64_t rvc_b_imm() { return (x(3, 4) << 1) + (x(2, 1) << 5) + (xs(10, 3) << 6); } uint64_t rvc_rd() { return rd(); } - uint64_t rvc_rs1() { return x(2, 5); } - uint64_t rvc_rs2() { return rd(); } - uint64_t rvc_rds() { return 8 + x(7, 3); } - uint64_t rvc_rs1s() { return 8 + x(2, 3); } - uint64_t rvc_rs2s() { return rvc_rds(); } + uint64_t rvc_rs1() { return rd(); } + uint64_t rvc_rs2() { return x(2, 5); } + uint64_t rvc_rds() { return 8 + x(10, 3); } + uint64_t rvc_rs1s() { return 8 + x(7, 3); } + uint64_t rvc_rs2s() { return 8 + x(2, 3); } private: insn_bits_t b; uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); } @@ -111,27 +118,30 @@ private: // helpful macros, etc #define MMU (*p->get_mmu()) #define STATE (*p->get_state()) -#define RS1 STATE.XPR[insn.rs1()] -#define RS2 STATE.XPR[insn.rs2()] +#define READ_REG(reg) STATE.XPR[reg] +#define RS1 READ_REG(insn.rs1()) +#define RS2 READ_REG(insn.rs2()) #define WRITE_REG(reg, value) STATE.XPR.write(reg, value) #define WRITE_RD(value) WRITE_REG(insn.rd(), value) #ifdef RISCV_ENABLE_COMMITLOG #undef WRITE_REG #define WRITE_REG(reg, value) ({ \ - reg_t wdata = value; /* value is a func with side-effects */ \ - STATE.log_reg_write = (commit_log_reg_t){reg << 1, wdata}; \ + reg_t wdata = (value); /* value is a func with side-effects */ \ + STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, wdata}; \ STATE.XPR.write(reg, wdata); \ }) #endif // RVC macros #define WRITE_RVC_RDS(value) WRITE_REG(insn.rvc_rds(), value) -#define RVC_RS1 STATE.XPR[insn.rvc_rs1()] -#define RVC_RS2 STATE.XPR[insn.rvc_rs2()] -#define RVC_RS1S STATE.XPR[insn.rvc_rs1s()] -#define RVC_RS2S STATE.XPR[insn.rvc_rs2s()] -#define RVC_SP STATE.XPR[2] +#define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value) +#define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value) +#define RVC_RS1 READ_REG(insn.rvc_rs1()) +#define RVC_RS2 READ_REG(insn.rvc_rs2()) +#define RVC_RS1S READ_REG(insn.rvc_rs1s()) +#define RVC_RS2S READ_REG(insn.rvc_rs2s()) +#define RVC_SP READ_REG(X_SP) // FPU macros #define FRS1 STATE.FPR[insn.rs1()] @@ -162,12 +172,13 @@ private: #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask))) -#define require_privilege(p) if (get_field(STATE.mstatus, MSTATUS_PRV) < (p)) throw trap_illegal_instruction() -#define require_rv64 if(unlikely(xlen != 64)) throw trap_illegal_instruction() -#define require_rv32 if(unlikely(xlen != 32)) throw trap_illegal_instruction() -#define require_extension(s) if (!p->supports_extension(s)) throw trap_illegal_instruction() -#define require_fp if (unlikely((STATE.mstatus & MSTATUS_FS) == 0)) throw trap_illegal_instruction() -#define require_accelerator if (unlikely((STATE.mstatus & MSTATUS_XS) == 0)) throw trap_illegal_instruction() +#define require(x) if (unlikely(!(x))) throw trap_illegal_instruction() +#define require_privilege(p) require(get_field(STATE.mstatus, MSTATUS_PRV) >= (p)) +#define require_rv64 require(xlen == 64) +#define require_rv32 require(xlen == 32) +#define require_extension(s) require(p->supports_extension(s)) +#define require_fp require((STATE.mstatus & MSTATUS_FS) != 0) +#define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0) #define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \ softfloat_exceptionFlags = 0; }) |