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| author | Andrew Waterman <waterman@eecs.berkeley.edu> | 2013-11-25 04:42:03 -0800 |
|---|---|---|
| committer | Andrew Waterman <waterman@eecs.berkeley.edu> | 2013-11-25 04:42:03 -0800 |
| commit | aedcd67ac8133ea71de7ff37b772c1533b038c93 (patch) | |
| tree | cbbed29e95894b53e2b751308f5805c881217937 /riscv/decode.h | |
| parent | ee7867e79ed0a80e23b3b1863adcb0dfd8427e1b (diff) | |
| download | spike-aedcd67ac8133ea71de7ff37b772c1533b038c93.zip spike-aedcd67ac8133ea71de7ff37b772c1533b038c93.tar.gz spike-aedcd67ac8133ea71de7ff37b772c1533b038c93.tar.bz2 | |
Update to new privileged ISA
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 3fc2be7..2229afb 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -10,7 +10,7 @@ #define __STDC_LIMIT_MACROS #include <stdint.h> #include <string.h> -#include "pcr.h" +#include "encoding.h" #include "config.h" #include "common.h" #include <cinttypes> @@ -48,8 +48,6 @@ const int NFPR = 32; #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) -#define FSR_ZERO ~(FSR_RD | FSR_AEXC) - class insn_t { public: @@ -131,7 +129,7 @@ private: #define BRANCH_TARGET (pc + insn.sb_imm()) #define JUMP_TARGET (pc + insn.uj_imm()) #define RM ({ int rm = insn.rm(); \ - if(rm == 7) rm = (p->get_state()->fsr & FSR_RD) >> FSR_RD_SHIFT; \ + if(rm == 7) rm = p->get_state()->frm; \ if(rm > 4) throw trap_illegal_instruction(); \ rm; }) @@ -148,8 +146,7 @@ private: #define require_accelerator if(unlikely(!(p->get_state()->sr & SR_EA))) throw trap_accelerator_disabled() #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen)) -#define set_fp_exceptions ({ p->set_fsr(p->get_state()->fsr | \ - (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \ +#define set_fp_exceptions ({ p->get_state()->fflags |= softfloat_exceptionFlags; \ softfloat_exceptionFlags = 0; }) #define sext32(x) ((sreg_t)(int32_t)(x)) @@ -169,4 +166,10 @@ private: npc = (x); \ } while(0) +#define validate_csr(which, write) ({ \ + int read_priv = ((which) >> 10) & 3; \ + int write_priv = ((which) >> 8) & 3; \ + if (read_priv > 0 || (write_priv > 0 && (write))) require_supervisor; \ + (which); }) + #endif |