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| author | Tim Newsome <tim@sifive.com> | 2016-05-01 12:05:48 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | 990c6c48098e83584edf5282d119187abae04a4d (patch) | |
| tree | d2ba581b281dce0c329822f98cc7c21faf868323 /riscv/decode.h | |
| parent | 57ff1b6595e485b8b002238ddbd10483bbd62fb3 (diff) | |
| download | spike-990c6c48098e83584edf5282d119187abae04a4d.zip spike-990c6c48098e83584edf5282d119187abae04a4d.tar.gz spike-990c6c48098e83584edf5282d119187abae04a4d.tar.bz2 | |
Have Debug memory kind of working again.
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 5732a0d..3a8b3a4 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -236,16 +236,16 @@ private: #define DCSR_CAUSE_STEPPED 4 #define DCSR_CAUSE_HALT 5 -#define DEBUG_START 0xfffffffffffff000 -#define DEBUG_ROM_START 0xfffffffffffff800 // TODO: 0x800 +#define DEBUG_START 0x100 +#define DEBUG_ROM_START 0x800 #define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4) #define DEBUG_ROM_END (DEBUG_ROM_START + debug_rom_raw_len) -#define DEBUG_RAM_START 0xfffffffffffffc00 // TODO: 0x400 +#define DEBUG_RAM_START 0x400 #define DEBUG_RAM_SIZE 64 #define DEBUG_RAM_END (DEBUG_RAM_START + DEBUG_RAM_SIZE) -#define DEBUG_END 0xffffffffffffffff -#define DEBUG_CLEARDEBINT 0xfffffffffffffef8 -#define DEBUG_SETHALTNOT 0xffffffffffffff00 +#define DEBUG_END 0xfff +#define DEBUG_CLEARDEBINT 0x108 +#define DEBUG_SETHALTNOT 0x100 #define DEBUG_SIZE (DEBUG_END - DEBUG_START + 1) #endif |