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| author | Tim Newsome <tim@sifive.com> | 2016-04-21 15:53:46 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:10 -0700 |
| commit | 5d1fb6b8c4eea6af9ebf02234724716ca25db3a1 (patch) | |
| tree | 9179a5250296f962a906a57fc4de09063fe76f5d /riscv/decode.h | |
| parent | cdf3116b6e107a21269751fc180ad0bb84c3960c (diff) | |
| download | spike-5d1fb6b8c4eea6af9ebf02234724716ca25db3a1.zip spike-5d1fb6b8c4eea6af9ebf02234724716ca25db3a1.tar.gz spike-5d1fb6b8c4eea6af9ebf02234724716ca25db3a1.tar.bz2 | |
Add writing to DCSR, DPC, DSCRATCH.
Make those 3 CSRs writable.
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 6e54431..b922e02 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -225,4 +225,9 @@ private: throw trap_illegal_instruction(); \ (which); }) +/* Debug CSRs. These should probably be in encoding.h, but that file is + * automatically generated. */ +/* TODO */ +#include "/media/sf_tnewsome/Synced/SiFive/debug-spec/core_registers.tex.h" + #endif |