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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-10-23 01:36:48 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-11 19:02:35 -0800 |
| commit | 4808f84a1833de2bbd87a92355f75991c4697312 (patch) | |
| tree | 464a74599559173af989a150973a76539d1ba663 /riscv/decode.h | |
| parent | e289b996c6ef60693b394b57bb53034c38eff4e4 (diff) | |
| download | spike-4808f84a1833de2bbd87a92355f75991c4697312.zip spike-4808f84a1833de2bbd87a92355f75991c4697312.tar.gz spike-4808f84a1833de2bbd87a92355f75991c4697312.tar.bz2 | |
rvv: add reg checking for specifial instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index dd98f8b..e19dffa 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -381,11 +381,6 @@ static inline bool is_overlapped(const int astart, const int asize, if (insn.v_vm() == 0) \ require(insn.rd() != 0); -#define VI_CHECK_VREG_OVERLAP(v1, v2) \ - require(!is_overlapped(v1, P.VU.vlmul, v2, P.VU.vlmul)); - -#define VI_CHECK_SS \ - require(!is_overlapped(insn.rd(), P.VU.vlmul, insn.rs2(), P.VU.vlmul)); #define VI_CHECK_MSS(is_vs1) \ if (P.VU.vlmul > 1) { \ require(!is_overlapped(insn.rd(), 1, insn.rs2(), P.VU.vlmul)); \ |