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| author | Andrew Waterman <andrew@sifive.com> | 2018-04-30 15:06:52 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-04-30 15:06:52 -0700 |
| commit | 3d016e2765f9ad5f34e471e345004c6e16438e3c (patch) | |
| tree | c9c03645fbd87502e8d18d7947518d83ea33b491 /riscv/decode.h | |
| parent | c0172e96bc2e83c990a22342ce7e99ba73142c47 (diff) | |
| download | spike-3d016e2765f9ad5f34e471e345004c6e16438e3c.zip spike-3d016e2765f9ad5f34e471e345004c6e16438e3c.tar.gz spike-3d016e2765f9ad5f34e471e345004c6e16438e3c.tar.bz2 | |
Only break out of the simulator loop on WFI, not on CSR writes
Breaking out of the loop on WFI was intended to let other threads run
when the current thread has no work to do. There's no advantage to doing
so on CSR writes, and the unintentional change in thread interleaving
broke some test programs that relied on short timer periods.
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 8fc8ada..9634f57 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -211,11 +211,17 @@ private: STATE.pc = __npc; \ } while(0) +#define wfi() \ + do { set_pc_and_serialize(npc); \ + npc = PC_SERIALIZE_WFI; \ + } while(0) + #define serialize() set_pc_and_serialize(npc) /* Sentinel PC values to serialize simulator pipeline */ #define PC_SERIALIZE_BEFORE 3 #define PC_SERIALIZE_AFTER 5 +#define PC_SERIALIZE_WFI 7 #define invalid_pc(pc) ((pc) & 1) /* Convenience wrappers to simplify softfloat code sequences */ |