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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-21 10:57:27 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-21 10:57:27 -0700 |
| commit | ff6a36f398ece668f4cca0583804aba0670ed87f (patch) | |
| tree | e5d3ccb9c9f6280982d76362b77554f15a120804 /riscv/decode.h | |
| parent | 264ae74af0ca320f9167662a810779c42e0153d4 (diff) | |
| download | spike-ff6a36f398ece668f4cca0583804aba0670ed87f.zip spike-ff6a36f398ece668f4cca0583804aba0670ed87f.tar.gz spike-ff6a36f398ece668f4cca0583804aba0670ed87f.tar.bz2 | |
rvv: fix index load/store emul/nf checking
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 76b9382..fa96ced 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -461,6 +461,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) require_align(insn.rd(), P.VU.vflmul); \ require_align(insn.rs2(), P.VU.vemul); \ require((nf * flmul) <= (NVPR / 4) && \ + (nf * emul) <= (NVPR / 4) && \ (insn.rd() + nf * flmul) <= NVPR && \ (insn.rs2() + nf * emul) <= NVPR); \ |