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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-03 20:24:49 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-03 22:48:23 -0800 |
| commit | eb6224d34a9847d3c8044464c57683efe85f5f7f (patch) | |
| tree | 1bab94d0928e3905e37159a4aa4b64f9e0d57db5 /riscv/decode.h | |
| parent | 7d761774f6351aba824ab1627a32e88779ae6956 (diff) | |
| download | spike-eb6224d34a9847d3c8044464c57683efe85f5f7f.zip spike-eb6224d34a9847d3c8044464c57683efe85f5f7f.tar.gz spike-eb6224d34a9847d3c8044464c57683efe85f5f7f.tar.bz2 | |
commitlog: enhance vector dump
1. don't duplicate vconfig for lmul >=2 case
2. add l# to show prenset vl value
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 6d6c1a5..2e0d649 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -231,6 +231,7 @@ private: require_vector_vs; \ require_extension('V'); \ require(!P.VU.vill); \ + STATE.log_reg_write[3] = {0, 0}; \ dirty_vs_state; \ } while (0); #define require_vector_for_vsetvl \ |