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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-03 23:32:09 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-03 23:32:09 -0800 |
| commit | e799cf99af80ebe6849bfda0d0af27906f21f3ce (patch) | |
| tree | 416b14da5a8324f2f666ff43fb6f081f65886c20 /riscv/decode.h | |
| parent | 1343338473f99dffe09a1ae827efb57863057e82 (diff) | |
| download | spike-e799cf99af80ebe6849bfda0d0af27906f21f3ce.zip spike-e799cf99af80ebe6849bfda0d0af27906f21f3ce.tar.gz spike-e799cf99af80ebe6849bfda0d0af27906f21f3ce.tar.bz2 | |
commitlog: fix conditional building error
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 2e0d649..d4ad98a 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -167,6 +167,7 @@ private: #ifndef RISCV_ENABLE_COMMITLOG # define WRITE_REG(reg, value) STATE.XPR.write(reg, value) # define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value)) +# define WRITE_VSTATUS #else /* 0 : int * 1 : floating @@ -182,6 +183,7 @@ private: STATE.log_reg_write[((reg) << 2) | 1] = wdata; \ DO_WRITE_FREG(reg, wdata); \ }) +# define WRITE_VSTATUS STATE.log_reg_write[3] = {0, 0}; #endif // RVC macros @@ -231,7 +233,7 @@ private: require_vector_vs; \ require_extension('V'); \ require(!P.VU.vill); \ - STATE.log_reg_write[3] = {0, 0}; \ + WRITE_VSTATUS; \ dirty_vs_state; \ } while (0); #define require_vector_for_vsetvl \ |