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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-11 22:56:02 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-11 22:59:52 -0700 |
| commit | e3cf508b426e072fbe6585148d5adbcdf0e6eb57 (patch) | |
| tree | 74a1935f91103f2eac8b4e6161b9432ee3be8328 /riscv/decode.h | |
| parent | 9352ff175ccfeb4c749cc4aa20bd7a4f12b71920 (diff) | |
| download | spike-e3cf508b426e072fbe6585148d5adbcdf0e6eb57.zip spike-e3cf508b426e072fbe6585148d5adbcdf0e6eb57.tar.gz spike-e3cf508b426e072fbe6585148d5adbcdf0e6eb57.tar.bz2 | |
commitlog: fix missing dump for some instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 2c8c3c0..8c8e7e6 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -564,7 +564,7 @@ static inline bool is_overlapped(const int astart, const int asize, uint64_t mmask = (UINT64_MAX << (64 - mlen)) >> (64 - mlen - mpos); \ uint64_t vs2 = P.VU.elt<uint64_t>(insn.rs2(), midx); \ uint64_t vs1 = P.VU.elt<uint64_t>(insn.rs1(), midx); \ - uint64_t &res = P.VU.elt<uint64_t>(insn.rd(), midx); \ + uint64_t &res = P.VU.elt<uint64_t>(insn.rd(), midx, true); \ res = (res & ~mmask) | ((op) & (1ULL << mpos)); \ } \ P.VU.vstart = 0; @@ -1133,19 +1133,19 @@ VI_LOOP_END switch(P.VU.vsew) { \ case e8: { \ sign_d##16_t vd_w = P.VU.elt<sign_d##16_t>(rd_num, i); \ - P.VU.elt<uint16_t>(rd_num, i) = \ + P.VU.elt<uint16_t>(rd_num, i, true) = \ op1((sign_1##16_t)(sign_1##8_t)var0 op0 (sign_2##16_t)(sign_2##8_t)var1) + var2; \ } \ break; \ case e16: { \ sign_d##32_t vd_w = P.VU.elt<sign_d##32_t>(rd_num, i); \ - P.VU.elt<uint32_t>(rd_num, i) = \ + P.VU.elt<uint32_t>(rd_num, i, true) = \ op1((sign_1##32_t)(sign_1##16_t)var0 op0 (sign_2##32_t)(sign_2##16_t)var1) + var2; \ } \ break; \ default: { \ sign_d##64_t vd_w = P.VU.elt<sign_d##64_t>(rd_num, i); \ - P.VU.elt<uint64_t>(rd_num, i) = \ + P.VU.elt<uint64_t>(rd_num, i, true) = \ op1((sign_1##64_t)(sign_1##32_t)var0 op0 (sign_2##64_t)(sign_2##32_t)var1) + var2; \ } \ break; \ |