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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-14 20:29:51 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-14 20:29:51 -0700 |
| commit | a2d2ade884e2673d67175bdc359b79cbb5942adf (patch) | |
| tree | 50ab49286cfd38871bf478c9808079643465cea2 /riscv/decode.h | |
| parent | c5ea4509557ad905f14855280476bdf27954120e (diff) | |
| download | spike-a2d2ade884e2673d67175bdc359b79cbb5942adf.zip spike-a2d2ade884e2673d67175bdc359b79cbb5942adf.tar.gz spike-a2d2ade884e2673d67175bdc359b79cbb5942adf.tar.bz2 | |
rvv: add vzext/vsext
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 4361466..e912789 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1756,6 +1756,38 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ } \ P.VU.vstart = 0; +// vector: sign/unsiged extension +#define VI_VV_EXT(div, type) \ + reg_t from = P.VU.vsew / div; \ + require(from >= e8 && from <= e64); \ + const reg_t mew = insn.v_mew(); \ + const reg_t width = insn.v_width(); \ + VI_EEW(mew, width); \ + VI_GENERAL_LOOP_BASE \ + switch (((P.VU.vsew >> 3) << 4)| from) { \ + case 0x21: \ + P.VU.elt<type##16_t>(rd_num, i, true) = P.VU.elt<type##8_t>(rs2_num, i); \ + break; \ + case 0x41: \ + P.VU.elt<type##32_t>(rd_num, i, true) = P.VU.elt<type##8_t>(rs2_num, i); \ + break; \ + case 0x81: \ + P.VU.elt<type##64_t>(rd_num, i, true) = P.VU.elt<type##8_t>(rs2_num, i); \ + break; \ + case 0x42: \ + P.VU.elt<type##32_t>(rd_num, i, true) = P.VU.elt<type##16_t>(rs2_num, i); \ + break; \ + case 0x82: \ + P.VU.elt<type##64_t>(rd_num, i, true) = P.VU.elt<type##16_t>(rs2_num, i); \ + break; \ + case 0x84: \ + P.VU.elt<type##64_t>(rd_num, i, true) = P.VU.elt<type##32_t>(rs2_num, i); \ + break; \ + default: \ + break; \ + } \ + VI_LOOP_END + // // vector: vfp helper // |