diff options
| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-18 21:00:47 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-18 21:00:47 -0700 |
| commit | 74b220698fb1a46e0279bba244de8b8ac3348403 (patch) | |
| tree | e596b63949a41febcc1a2a4592049e440798497a /riscv/decode.h | |
| parent | 0384db6749c3e631be50cac308d55f57a1abdc41 (diff) | |
| download | spike-74b220698fb1a46e0279bba244de8b8ac3348403.zip spike-74b220698fb1a46e0279bba244de8b8ac3348403.tar.gz spike-74b220698fb1a46e0279bba244de8b8ac3348403.tar.bz2 | |
rvv: fix compiler warning
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 2bd11a6..f547ec8 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1707,7 +1707,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ const reg_t baseAddr = RS1; \ const reg_t vd = insn.rd(); \ const reg_t rs2_num = insn.rs2(); \ - require(P.VU.vsew >= xlen && P.VU.vsew <= xlen); \ + require(P.VU.vsew >= P.get_xlen() && P.VU.vsew <= P.get_xlen()); \ for (reg_t i = P.VU.vstart; i < vl; ++i) { \ VI_ELEMENT_SKIP(i); \ VI_STRIP(i); \ |