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authorChih-Min Chao <chihmin.chao@sifive.com>2020-05-20 00:05:12 -0700
committerChih-Min Chao <chihmin.chao@sifive.com>2020-05-20 00:09:57 -0700
commit67fc0f5d6be03929b412aa70d47236d67f68b769 (patch)
tree71156bc51760815369f7d435e144cb2ded2e4b13 /riscv/decode.h
parent770db4aedac6a7812a0c34b9ac717a517722826d (diff)
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rvv: fix out of range checking unit/strided
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
-rw-r--r--riscv/decode.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/decode.h b/riscv/decode.h
index 8d3968f..9eb4058 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -484,9 +484,9 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
require_vector; \
P.VU.veew = sizeof(elt_width##_t) * 8; \
P.VU.vemul = ((float)P.VU.veew / P.VU.vsew * P.VU.vflmul); \
- reg_t emul = P.VU.vemul + 0.875; \
- require(emul >= 1 && emul <= 8); \
- require_align(insn.rd(), P.VU.vflmul); \
+ reg_t emul = P.VU.vemul < 1 ? 1 : P.VU.vemul; \
+ require(P.VU.vemul >= 0.125 && P.VU.vemul <= 8); \
+ require_align(insn.rd(), P.VU.vemul); \
require((nf * emul) <= (NVPR / 4) && \
(insn.rd() + nf * emul) <= NVPR); \