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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-27 19:53:37 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-27 20:15:02 -0700 |
| commit | 6657a560699e2e2da1a3b8e86a227d2929a3dc5b (patch) | |
| tree | c4fb3dc7b8fbf2d9d72530b7b10b0c0ec34aa036 /riscv/decode.h | |
| parent | dfaec7ba7863e236e4d7e4376a3957d6b6482a39 (diff) | |
| download | spike-6657a560699e2e2da1a3b8e86a227d2929a3dc5b.zip spike-6657a560699e2e2da1a3b8e86a227d2929a3dc5b.tar.gz spike-6657a560699e2e2da1a3b8e86a227d2929a3dc5b.tar.bz2 | |
rvv: align VCSR with upstream
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index bf0d143..9c69b48 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -34,11 +34,11 @@ const int NCSR = 4096; #define X_RA 1 #define X_SP 2 -#define VSR_VXRM_SHIFT 1 -#define VSR_VXRM (0x3 << VSR_VXRM_SHIFT) +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT) -#define VSR_VXSAT_SHIFT 0 -#define VSR_VXSAT (0x1 << VSR_VXSAT_SHIFT) +#define VCSR_VXSAT_SHIFT 0 +#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT) #define FP_RD_NE 0 #define FP_RD_0 1 |