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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-21 20:35:32 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-21 21:30:18 -0700 |
| commit | 3f7c06a2b25ebf033d2ad233c1ccde1f833b2e55 (patch) | |
| tree | 32d1a3c5dd44216f02010d92f1beda807482c2ea /riscv/decode.h | |
| parent | a64159ffc6816ec2e20006ff9c1d1cc9a5a518e2 (diff) | |
| download | spike-3f7c06a2b25ebf033d2ad233c1ccde1f833b2e55.zip spike-3f7c06a2b25ebf033d2ad233c1ccde1f833b2e55.tar.gz spike-3f7c06a2b25ebf033d2ad233c1ccde1f833b2e55.tar.bz2 | |
rvv: fix floating comparison for fp16
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 33 |
1 files changed, 22 insertions, 11 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 2d923b1..f9c3bc8 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1689,19 +1689,18 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \ #define VI_VFP_LOOP_CMP_END \ switch(P.VU.vsew) { \ + case e16: \ case e32: \ case e64: { \ vdi = (vdi & ~mmask) | (((res) << mpos) & mmask); \ break; \ } \ - case e16: \ default: \ require(0); \ break; \ }; \ } \ - P.VU.vstart = 0; \ - set_fp_exceptions; + P.VU.vstart = 0; #define VI_VFP_VV_LOOP(BODY16, BODY32, BODY64) \ VI_CHECK_SSS(true); \ @@ -1927,20 +1926,26 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \ }; \ VI_VFP_LOOP_CMP_END \ -#define VI_VFP_VF_LOOP_WIDE(BODY) \ +#define VI_VFP_VF_LOOP_WIDE(BODY16, BODY32) \ VI_CHECK_DSS(false); \ VI_VFP_LOOP_BASE \ switch(P.VU.vsew) { \ + case e16: { \ + float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \ + float32_t vs2 = f16_to_f32(P.VU.elt<float16_t>(rs2_num, i)); \ + float32_t rs1 = f16_to_f32(f16(READ_FREG(rs1_num))); \ + BODY16; \ + set_fp_exceptions; \ + break; \ + } \ case e32: {\ float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \ float64_t vs2 = f32_to_f64(P.VU.elt<float32_t>(rs2_num, i)); \ float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \ - BODY; \ + BODY32; \ set_fp_exceptions; \ break; \ }\ - case e16: \ - case e8: \ default: \ require(0); \ break; \ @@ -1970,20 +1975,26 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \ DEBUG_RVV_FP_VV; \ VI_VFP_LOOP_END -#define VI_VFP_WF_LOOP_WIDE(BODY) \ +#define VI_VFP_WF_LOOP_WIDE(BODY16, BODY32) \ VI_CHECK_DDS(false); \ VI_VFP_LOOP_BASE \ switch(P.VU.vsew) { \ + case e16: {\ + float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \ + float32_t vs2 = P.VU.elt<float32_t>(rs2_num, i); \ + float32_t rs1 = f16_to_f32(f16(READ_FREG(rs1_num))); \ + BODY16; \ + set_fp_exceptions; \ + break; \ + }\ case e32: {\ float64_t &vd = P.VU.elt<float64_t>(rd_num, i, true); \ float64_t vs2 = P.VU.elt<float64_t>(rs2_num, i); \ float64_t rs1 = f32_to_f64(f32(READ_FREG(rs1_num))); \ - BODY; \ + BODY32; \ set_fp_exceptions; \ break; \ }\ - case e16: \ - case e8: \ default: \ require(0); \ }; \ |