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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-14 21:28:53 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-14 21:28:53 -0700 |
| commit | 19834b39e53affb7ae6fae7c8405e36995b33ed4 (patch) | |
| tree | 8f39cf26d49b3c7ed5daafdac52582fae50366c0 /riscv/decode.h | |
| parent | a2d2ade884e2673d67175bdc359b79cbb5942adf (diff) | |
| download | spike-19834b39e53affb7ae6fae7c8405e36995b33ed4.zip spike-19834b39e53affb7ae6fae7c8405e36995b33ed4.tar.gz spike-19834b39e53affb7ae6fae7c8405e36995b33ed4.tar.bz2 | |
rvv: amo: only allow 32/64 bit element
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 15 |
1 files changed, 1 insertions, 14 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index e912789..9d6b7be 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1717,24 +1717,11 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ const reg_t baseAddr = RS1; \ const reg_t vd = insn.rd(); \ const reg_t rs2_num = insn.rs2(); \ + require(P.VU.vsew >= xlen && P.VU.vsew <= xlen); \ for (reg_t i = P.VU.vstart; i < vl; ++i) { \ VI_ELEMENT_SKIP(i); \ VI_STRIP(i); \ switch (P.VU.vsew) { \ - case e8: {\ - auto vs3 = P.VU.elt< type ## 8_t>(vd, vreg_inx); \ - auto val = MMU.amo_uint8(baseAddr + index[i], [&]( type ## 8_t lhs) { op }); \ - if (insn.v_wd()) \ - P.VU.elt< type ## 8_t>(vd, vreg_inx, true) = val; \ - } \ - break; \ - case e16: {\ - auto vs3 = P.VU.elt< type ## 16_t>(vd, vreg_inx); \ - auto val = MMU.amo_uint16(baseAddr + index[i], [&]( type ## 16_t lhs) { op }); \ - if (insn.v_wd()) \ - P.VU.elt< type ## 16_t>(vd, vreg_inx, true) = val; \ - } \ - break; \ case e32: {\ auto vs3 = P.VU.elt< type ## 32_t>(vd, vreg_inx); \ auto val = MMU.amo_uint32(baseAddr + index[i], [&]( type ## 32_t lhs) { op }); \ |