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| author | Andrew Waterman <andrew@sifive.com> | 2022-01-06 17:19:11 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-01-06 17:21:06 -0800 |
| commit | fc572daaef35fdc081466e6a67413b1f3b4d6a3e (patch) | |
| tree | 1b13e962055a28f0d3044720f2f6e2b05c3addfc /riscv/decode.h | |
| parent | 2fbc6cde0b6b0e7d4ef77ae092c4ae286a77e2bf (diff) | |
| download | spike-fc572daaef35fdc081466e6a67413b1f3b4d6a3e.zip spike-fc572daaef35fdc081466e6a67413b1f3b4d6a3e.tar.gz spike-fc572daaef35fdc081466e6a67413b1f3b4d6a3e.tar.bz2 | |
Support RV32E/RV64E base ISAs
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 3b3cf54..0365047 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -175,7 +175,8 @@ private: #define MMU (*p->get_mmu()) #define STATE (*p->get_state()) #define FLEN (p->get_flen()) -#define READ_REG(reg) STATE.XPR[reg] +#define CHECK_REG(reg) ((void) 0) +#define READ_REG(reg) ({ CHECK_REG(reg); STATE.XPR[reg]; }) #define READ_FREG(reg) STATE.FPR[reg] #define RD READ_REG(insn.rd()) #define RS1 READ_REG(insn.rs1()) @@ -184,7 +185,7 @@ private: #define WRITE_RD(value) WRITE_REG(insn.rd(), value) #ifndef RISCV_ENABLE_COMMITLOG -# define WRITE_REG(reg, value) STATE.XPR.write(reg, value) +# define WRITE_REG(reg, value) ({ CHECK_REG(reg); STATE.XPR.write(reg, value); }) # define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value)) # define WRITE_VSTATUS #else @@ -197,6 +198,7 @@ private: # define WRITE_REG(reg, value) ({ \ reg_t wdata = (value); /* value may have side effects */ \ STATE.log_reg_write[(reg) << 4] = {wdata, 0}; \ + CHECK_REG(reg); \ STATE.XPR.write(reg, wdata); \ }) # define WRITE_FREG(reg, value) ({ \ |