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| author | Andrew Waterman <andrew@sifive.com> | 2022-01-09 17:04:17 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-01-09 17:05:07 -0800 |
| commit | d1a3a4255295b742728b8c851a222cfbf06e8116 (patch) | |
| tree | 22b1f5d3175faff032308b4f4cc1bb187cc9498d /riscv/decode.h | |
| parent | 39fc8c3921e8c9ffd9996a7d59df239b2488a206 (diff) | |
| download | spike-d1a3a4255295b742728b8c851a222cfbf06e8116.zip spike-d1a3a4255295b742728b8c851a222cfbf06e8116.tar.gz spike-d1a3a4255295b742728b8c851a222cfbf06e8116.tar.bz2 | |
Changes to be cleaner wrt. -Wextra
h/t @jerinjoy
See #901
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 3b3cf54..e709d03 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -186,7 +186,7 @@ private: #ifndef RISCV_ENABLE_COMMITLOG # define WRITE_REG(reg, value) STATE.XPR.write(reg, value) # define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value)) -# define WRITE_VSTATUS +# define WRITE_VSTATUS {} #else /* 0 : int * 1 : floating |