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| author | eopXD <yueh.ting.chen@gmail.com> | 2021-12-09 10:33:28 +0800 |
|---|---|---|
| committer | eopXD <yueh.ting.chen@gmail.com> | 2021-12-09 18:59:33 +0800 |
| commit | 95c06fbc24c7745941689dae37f7d94faddfa8f5 (patch) | |
| tree | 65f4e620e2164ab20acdcf39ba34029a88a0797b /riscv/decode.h | |
| parent | 381b28d6340300e4acbc80b19c8d690fc124450e (diff) | |
| download | spike-95c06fbc24c7745941689dae37f7d94faddfa8f5.zip spike-95c06fbc24c7745941689dae37f7d94faddfa8f5.tar.gz spike-95c06fbc24c7745941689dae37f7d94faddfa8f5.tar.bz2 | |
Simplify vfncvt
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 1d6ea9a..5f566ce 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -852,6 +852,18 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) float##width##_t rs1 = f##width(READ_FREG(rs1_num)); \ float##width##_t vs2 = P.VU.elt<float##width##_t>(rs2_num, i); +#define CVT_FP_TO_FP_PARAMS(from_width, to_width) \ + auto vs2 = P.VU.elt<float##from_width##_t>(rs2_num, i); \ + auto &vd = P.VU.elt<float##to_width##_t>(rd_num, i, true); + +#define CVT_INT_TO_FP_PARAMS(from_width, to_width, sign) \ + auto vs2 = P.VU.elt<sign##from_width##_t>(rs2_num, i); \ + auto &vd = P.VU.elt<float##to_width##_t>(rd_num, i, true); + +#define CVT_FP_TO_INT_PARAMS(from_width, to_width, sign) \ + auto vs2 = P.VU.elt<float##from_width##_t>(rs2_num, i); \ + auto &vd = P.VU.elt<sign##to_width##_t>(rd_num, i, true); + // // vector: integer and masking operation loop // @@ -2369,6 +2381,64 @@ reg_t index[P.VU.vlmax]; \ for (reg_t i=P.VU.vstart->read(); i<vl; ++i){ \ VI_LOOP_ELEMENT_SKIP(); +#define VI_VFP_CVT_LOOP(CVT_PARAMS, CHECK, BODY) \ + CHECK \ + VI_VFP_LOOP_SCALE_BASE \ + CVT_PARAMS \ + BODY \ + set_fp_exceptions; \ + VI_VFP_LOOP_END + +#define VI_VFP_NCVT_FP_TO_FP(BODY8, BODY16, BODY32, \ + CHECK8, CHECK16, CHECK32) \ + VI_CHECK_SDS(false); \ + switch(P.VU.vsew) { \ + case e16: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(32, 16), CHECK16, BODY16); } \ + break; \ + case e32: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_FP_PARAMS(64, 32), CHECK32, BODY32); } \ + break; \ + default: \ + require(0); \ + break; \ + } + +#define VI_VFP_NCVT_INT_TO_FP(BODY8, BODY16, BODY32, \ + CHECK8, CHECK16, CHECK32, \ + sign) \ + VI_CHECK_SDS(false); \ + switch(P.VU.vsew) { \ + case e16: \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(32, 16, sign), CHECK16, BODY16); } \ + break; \ + case e32: \ + { VI_VFP_CVT_LOOP(CVT_INT_TO_FP_PARAMS(64, 32, sign), CHECK32, BODY32); } \ + break; \ + default: \ + require(0); \ + break; \ + } + +#define VI_VFP_NCVT_FP_TO_INT(BODY8, BODY16, BODY32, \ + CHECK8, CHECK16, CHECK32, \ + sign) \ + VI_CHECK_SDS(false); \ + switch(P.VU.vsew) { \ + case e8: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(16, 8, sign), CHECK8, BODY8); } \ + break; \ + case e16: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(32, 16, sign), CHECK16, BODY16); } \ + break; \ + case e32: \ + { VI_VFP_CVT_LOOP(CVT_FP_TO_INT_PARAMS(64, 32, sign), CHECK32, BODY32); } \ + break; \ + default: \ + require(0); \ + break; \ + } + #define VI_VFP_CVT_SCALE(BODY8, BODY16, BODY32, \ CHECK8, CHECK16, CHECK32, \ is_widen, eew_check) \ |