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| author | Scott Johnson <scott.johnson@arilinc.com> | 2021-10-06 09:25:17 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2021-10-06 09:25:17 -0700 |
| commit | 2e873ce98e7afc0304cffe8f6ea2d7afea8efc2a (patch) | |
| tree | 46b4718b1cb4029eaf6dddfb1d6ca06cbf9b696d /riscv/decode.h | |
| parent | bcab7c19ed4cf997f6c55587b0481f32b3a612f4 (diff) | |
| download | spike-2e873ce98e7afc0304cffe8f6ea2d7afea8efc2a.zip spike-2e873ce98e7afc0304cffe8f6ea2d7afea8efc2a.tar.gz spike-2e873ce98e7afc0304cffe8f6ea2d7afea8efc2a.tar.bz2 | |
Don't write vxsat unless it's actually being set to 1
As requested by @marcfedorow:
https://github.com/riscv-software-src/riscv-isa-sim/issues/823#issuecomment-936509476
If mstatus.VS exists (i.e. Vector extension is enabled), it will no
longer be set to Dirty unless the instruction actually sets vxsat.
The mstatus.VS change only affects instructions in the P extension,
since Vector instructions will write other vector state and therefore
still set mstatus.VS=Dirty.
This also affects the commit log. Instructions that don't saturate
will no longer show a write to vxsat.
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 7028c85..3c192a5 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -2343,7 +2343,7 @@ reg_t index[P.VU.vlmax]; \ } #define P_SET_OV(ov) \ - P.VU.vxsat->write(P.VU.vxsat->read() | ov); + if (ov) P.VU.vxsat->write(1); #define P_SAT(R, BIT) \ if (R > INT##BIT##_MAX) { \ |