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author | eopXD <yueh.ting.chen@gmail.com> | 2021-12-07 23:55:19 +0800 |
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committer | eopXD <yueh.ting.chen@gmail.com> | 2021-12-08 01:22:10 +0800 |
commit | 1f06e0ecaafb94c595805ad036ccb07affb479f5 (patch) | |
tree | 479b83f2b0fd1ddefebaf10567782ffa40cceebd /riscv/decode.h | |
parent | 626fce2075e7907583e07f72f16187d6915ae84d (diff) | |
download | spike-1f06e0ecaafb94c595805ad036ccb07affb479f5.zip spike-1f06e0ecaafb94c595805ad036ccb07affb479f5.tar.gz spike-1f06e0ecaafb94c595805ad036ccb07affb479f5.tar.bz2 |
Simplify vmerge, vfmerge
Diffstat (limited to 'riscv/decode.h')
-rw-r--r-- | riscv/decode.h | 71 |
1 files changed, 66 insertions, 5 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index d3cb558..f593414 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -960,23 +960,84 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) VI_LOOP_CMP_END // merge and copy loop -#define VI_VVXI_MERGE_LOOP(BODY) \ +#define VI_MERGE_VARS \ + VI_MASK_VARS \ + bool use_first = (P.VU.elt<uint64_t>(0, midx) >> mpos) & 0x1; + +#define VI_MERGE_LOOP_BASE \ + require_vector(true); \ VI_GENERAL_LOOP_BASE \ + VI_MERGE_VARS + +#define VI_VV_MERGE_LOOP(BODY) \ + VI_CHECK_SSS(true); \ + VI_MERGE_LOOP_BASE \ if (sew == e8){ \ - VXI_PARAMS(e8); \ + VV_PARAMS(e8); \ BODY; \ }else if(sew == e16){ \ - VXI_PARAMS(e16); \ + VV_PARAMS(e16); \ BODY; \ }else if(sew == e32){ \ - VXI_PARAMS(e32); \ + VV_PARAMS(e32); \ BODY; \ }else if(sew == e64){ \ - VXI_PARAMS(e64); \ + VV_PARAMS(e64); \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VX_MERGE_LOOP(BODY) \ + VI_CHECK_SSS(false); \ + VI_MERGE_LOOP_BASE \ + if (sew == e8){ \ + VX_PARAMS(e8); \ + BODY; \ + }else if(sew == e16){ \ + VX_PARAMS(e16); \ + BODY; \ + }else if(sew == e32){ \ + VX_PARAMS(e32); \ + BODY; \ + }else if(sew == e64){ \ + VX_PARAMS(e64); \ BODY; \ } \ VI_LOOP_END +#define VI_VI_MERGE_LOOP(BODY) \ + VI_CHECK_SSS(false); \ + VI_MERGE_LOOP_BASE \ + if (sew == e8){ \ + VI_PARAMS(e8); \ + BODY; \ + }else if(sew == e16){ \ + VI_PARAMS(e16); \ + BODY; \ + }else if(sew == e32){ \ + VI_PARAMS(e32); \ + BODY; \ + }else if(sew == e64){ \ + VI_PARAMS(e64); \ + BODY; \ + } \ + VI_LOOP_END + +#define VI_VF_MERGE_LOOP(BODY) \ + VI_CHECK_SSS(false); \ + VI_MERGE_LOOP_BASE \ + if(sew == e16){ \ + VFP_VF_PARAMS(16); \ + BODY; \ + }else if(sew == e32){ \ + VFP_VF_PARAMS(32); \ + BODY; \ + }else if(sew == e64){ \ + VFP_VF_PARAMS(64); \ + BODY; \ + } \ + VI_LOOP_END + // reduction loop - signed #define VI_LOOP_REDUCTION_BASE(x) \ require(x >= e8 && x <= e64); \ |