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authorChih-Min Chao <chihmin.chao@sifive.com>2020-04-01 01:06:49 -0700
committerChih-Min Chao <chihmin.chao@sifive.com>2020-05-04 09:50:05 -0700
commitaaf76d8430c110df9414cb3b39b5c0bd48300853 (patch)
tree3c9a70f3b35efdf07506fd78f98e2ad5544f04a7 /riscv/decode.h
parentb216e03dd1c10d17693053a1eb83a20fff3242ea (diff)
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rvv: fp16: support .vf instructions
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
-rw-r--r--riscv/decode.h12
1 files changed, 9 insertions, 3 deletions
diff --git a/riscv/decode.h b/riscv/decode.h
index f455759..e2bb69e 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -1797,10 +1797,18 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
DEBUG_RVV_FP_VV; \
VI_VFP_LOOP_REDUCTION_END(e64)
-#define VI_VFP_VF_LOOP(BODY32, BODY64) \
+#define VI_VFP_VF_LOOP(BODY16, BODY32, BODY64) \
VI_CHECK_SSS(false); \
VI_VFP_LOOP_BASE \
switch(P.VU.vsew) { \
+ case e16: {\
+ float16_t &vd = P.VU.elt<float16_t>(rd_num, i, true); \
+ float16_t rs1 = f16(READ_FREG(rs1_num)); \
+ float16_t vs2 = P.VU.elt<float16_t>(rs2_num, i); \
+ BODY16; \
+ set_fp_exceptions; \
+ break; \
+ }\
case e32: {\
float32_t &vd = P.VU.elt<float32_t>(rd_num, i, true); \
float32_t rs1 = f32(READ_FREG(rs1_num)); \
@@ -1817,8 +1825,6 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
set_fp_exceptions; \
break; \
}\
- case e16: \
- case e8: \
default: \
require(0); \
break; \