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| author | Andrew Waterman <andrew@sifive.com> | 2020-02-18 18:37:04 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-18 18:37:04 -0800 |
| commit | 78bbcb94c25b15e27d7414db2a121d28c57d7af0 (patch) | |
| tree | 68921f170ce4e16d4c102c155f64ee1a0e218203 /riscv/decode.h | |
| parent | 722b9bf869b7928b060201a794406bcf32a4d532 (diff) | |
| download | spike-78bbcb94c25b15e27d7414db2a121d28c57d7af0.zip spike-78bbcb94c25b15e27d7414db2a121d28c57d7af0.tar.gz spike-78bbcb94c25b15e27d7414db2a121d28c57d7af0.tar.bz2 | |
Vector stores don't care if rd overlaps v0 (#400)
Since vector stores read rd, rather than write rd, there is no overlap
constraint.
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 25 |
1 files changed, 16 insertions, 9 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 505cda5..bbcc37a 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -415,7 +415,7 @@ static inline bool is_overlapped(const int astart, const int asize, if (insn.v_vm() == 0) \ require(insn.rd() != 0); -#define VI_CHECK_LDST_INDEX \ +#define VI_CHECK_ST_INDEX \ require_vector; \ require((insn.rd() & (P.VU.vlmul - 1)) == 0); \ require((insn.rs2() & (P.VU.vlmul - 1)) == 0); \ @@ -424,6 +424,11 @@ static inline bool is_overlapped(const int astart, const int asize, if (insn.v_vm() == 0 && (insn.v_nf() > 0 || P.VU.vlmul > 1)) \ require(insn.rd() != 0); \ +#define VI_CHECK_LD_INDEX \ + VI_CHECK_ST_INDEX; \ + if (insn.v_vm() == 0 && (insn.v_nf() > 0 || P.VU.vlmul > 1)) \ + require(insn.rd() != 0); \ + #define VI_CHECK_MSS(is_vs1) \ if (P.VU.vlmul > 1) { \ require(!is_overlapped(insn.rd(), 1, insn.rs2(), P.VU.vlmul)); \ @@ -445,12 +450,14 @@ static inline bool is_overlapped(const int astart, const int asize, require(insn.rd() != 0); \ } -#define VI_CHECK_SXX \ +#define VI_CHECK_STORE_SXX \ require_vector; \ - if (P.VU.vlmul > 1) { \ - require((insn.rd() & (P.VU.vlmul - 1)) == 0); \ - if (insn.v_vm() == 0) \ - require(insn.rd() != 0); \ + require((insn.rd() & (P.VU.vlmul - 1)) == 0); + +#define VI_CHECK_SXX \ + VI_CHECK_STORE_SXX; \ + if (P.VU.vlmul > 1 && insn.v_vm() == 0) { \ + require(insn.rd() != 0); \ } #define VI_CHECK_DSS(is_vs1) \ @@ -1540,15 +1547,15 @@ for (reg_t i = 0; i < vlmax; ++i) { \ VI_LD_COMMON(stride, offset, ld_width, elt_byte) #define VI_LD_INDEX(stride, offset, ld_width, elt_byte) \ - VI_CHECK_LDST_INDEX; \ + VI_CHECK_LD_INDEX; \ VI_LD_COMMON(stride, offset, ld_width, elt_byte) #define VI_ST(stride, offset, st_width, elt_byte) \ - VI_CHECK_SXX; \ + VI_CHECK_STORE_SXX; \ VI_ST_COMMON(stride, offset, st_width, elt_byte) \ #define VI_ST_INDEX(stride, offset, st_width, elt_byte) \ - VI_CHECK_LDST_INDEX; \ + VI_CHECK_ST_INDEX; \ VI_ST_COMMON(stride, offset, st_width, elt_byte) \ #define VI_LDST_FF(itype, tsew) \ |