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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-02 00:03:17 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-02 21:24:19 -0700 |
| commit | 3e9c9f75e9720ce5ce2c2b41e5defd9dad9d4915 (patch) | |
| tree | d6d0d7aa29cc5966c3afead8b21e3bca5c9cb1ee /riscv/decode.h | |
| parent | 0884e5bbd77a4df950c2ccfff78ad157ffcec631 (diff) | |
| download | spike-3e9c9f75e9720ce5ce2c2b41e5defd9dad9d4915.zip spike-3e9c9f75e9720ce5ce2c2b41e5defd9dad9d4915.tar.gz spike-3e9c9f75e9720ce5ce2c2b41e5defd9dad9d4915.tar.bz2 | |
commitlog: extend hint bit to record csr access
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 71caa58..34fa1d2 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -180,16 +180,18 @@ private: #else /* 0 : int * 1 : floating - * 2 : vector + * 2 : vector reg + * 3 : vector hint + * 4 : csr */ # define WRITE_REG(reg, value) ({ \ reg_t wdata = (value); /* value may have side effects */ \ - STATE.log_reg_write[(reg) << 2] = {wdata, 0}; \ + STATE.log_reg_write[(reg) << 4] = {wdata, 0}; \ STATE.XPR.write(reg, wdata); \ }) # define WRITE_FREG(reg, value) ({ \ freg_t wdata = freg(value); /* value may have side effects */ \ - STATE.log_reg_write[((reg) << 2) | 1] = wdata; \ + STATE.log_reg_write[((reg) << 4) | 1] = wdata; \ DO_WRITE_FREG(reg, wdata); \ }) # define WRITE_VSTATUS STATE.log_reg_write[3] = {0, 0}; |