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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-03 20:24:49 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-03-09 19:59:47 -0700 |
| commit | 2be050171015bb662a4495422c9e31f0be8a9c3a (patch) | |
| tree | ee2ba637dab51239bbc3294175fd16c9ce30d518 /riscv/decode.h | |
| parent | c949a75893a3c8df98a407d216ee995c82d4db4f (diff) | |
| download | spike-2be050171015bb662a4495422c9e31f0be8a9c3a.zip spike-2be050171015bb662a4495422c9e31f0be8a9c3a.tar.gz spike-2be050171015bb662a4495422c9e31f0be8a9c3a.tar.bz2 | |
commitlog: enhance vector dump
1. don't duplicate vconfig for lmul >=2 case
2. add l# to show prenset vl value
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/decode.h')
| -rw-r--r-- | riscv/decode.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 0dd6975..73514dc 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -167,6 +167,7 @@ private: #ifndef RISCV_ENABLE_COMMITLOG # define WRITE_REG(reg, value) STATE.XPR.write(reg, value) # define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value)) +# define WRITE_VSTATUS #else /* 0 : int * 1 : floating @@ -182,6 +183,7 @@ private: STATE.log_reg_write[((reg) << 2) | 1] = wdata; \ DO_WRITE_FREG(reg, wdata); \ }) +# define WRITE_VSTATUS STATE.log_reg_write[3] = {0, 0}; #endif // RVC macros @@ -231,6 +233,7 @@ private: require_vector_vs; \ require_extension('V'); \ require(!P.VU.vill); \ + WRITE_VSTATUS; \ dirty_vs_state; \ } while (0); #define require_vector_for_vsetvl \ |