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| author | Tim Newsome <tim@sifive.com> | 2016-05-01 12:05:48 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
| commit | 990c6c48098e83584edf5282d119187abae04a4d (patch) | |
| tree | d2ba581b281dce0c329822f98cc7c21faf868323 /riscv/debug_module.h | |
| parent | 57ff1b6595e485b8b002238ddbd10483bbd62fb3 (diff) | |
| download | spike-990c6c48098e83584edf5282d119187abae04a4d.zip spike-990c6c48098e83584edf5282d119187abae04a4d.tar.gz spike-990c6c48098e83584edf5282d119187abae04a4d.tar.bz2 | |
Have Debug memory kind of working again.
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
Diffstat (limited to 'riscv/debug_module.h')
| -rw-r--r-- | riscv/debug_module.h | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/riscv/debug_module.h b/riscv/debug_module.h index 734a2a3..d7c1a87 100644 --- a/riscv/debug_module.h +++ b/riscv/debug_module.h @@ -9,11 +9,8 @@ class debug_module_t : public abstract_device_t { public: - debug_module_t(); - bool load(reg_t addr, size_t len, uint8_t* bytes); bool store(reg_t addr, size_t len, const uint8_t* bytes); - char* page(reg_t paddr); void ram_write32(unsigned int index, uint32_t value); uint32_t ram_read32(unsigned int index); @@ -33,8 +30,7 @@ class debug_module_t : public abstract_device_t private: // Track which interrupts from module to debugger are set. std::set<uint32_t> interrupt; - // TODO: use PGSIZE, which requires solving some circular include dependencies. - char raw_page[4096]; + char debug_ram[DEBUG_RAM_SIZE]; }; #endif |