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| author | Tim Newsome <tim@sifive.com> | 2017-02-15 19:05:20 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-02-15 19:05:20 -0800 |
| commit | f88504000a7c7a16685dc59bdbb9be314a35d0b2 (patch) | |
| tree | ceb3f357a2e5c004c4bf1f859847dab4625418d4 /riscv/debug_module.h | |
| parent | 4df7f6d279314ccf78d14c482a9f04e49e0e0b47 (diff) | |
| download | spike-f88504000a7c7a16685dc59bdbb9be314a35d0b2.zip spike-f88504000a7c7a16685dc59bdbb9be314a35d0b2.tar.gz spike-f88504000a7c7a16685dc59bdbb9be314a35d0b2.tar.bz2 | |
Implement autoexec. DMI op 2 is just write now.
Now passing MemTest{8,16,32,64}
Diffstat (limited to 'riscv/debug_module.h')
| -rw-r--r-- | riscv/debug_module.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/debug_module.h b/riscv/debug_module.h index 7d9b3aa..76bcf01 100644 --- a/riscv/debug_module.h +++ b/riscv/debug_module.h @@ -126,10 +126,11 @@ class debug_module_t : public abstract_device_t dmcontrol_t dmcontrol; abstractcs_t abstractcs; + uint32_t command; processor_t *current_proc() const; void reset(); - bool perform_abstract_command(uint32_t command); + bool perform_abstract_command(); }; #endif |