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| author | Tim Newsome <tim@sifive.com> | 2017-02-15 20:41:06 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-02-15 20:41:06 -0800 |
| commit | 8dd673b74499d0195f6b1308a6709e05db6fa571 (patch) | |
| tree | 4abbe94e532cf3af9ee8b8aca45088ba31eb78bb /riscv/debug_module.cc | |
| parent | f88504000a7c7a16685dc59bdbb9be314a35d0b2 (diff) | |
| download | spike-8dd673b74499d0195f6b1308a6709e05db6fa571.zip spike-8dd673b74499d0195f6b1308a6709e05db6fa571.tar.gz spike-8dd673b74499d0195f6b1308a6709e05db6fa571.tar.bz2 | |
Set cmderr when data is accessed while busy.
Diffstat (limited to 'riscv/debug_module.cc')
| -rw-r--r-- | riscv/debug_module.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 8d93e9e..af71974 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -221,6 +221,10 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) unsigned i = address - DMI_DATA0; result = dmdata.read32(4 * i); + if (abstractcs.busy && abstractcs.cmderr == abstractcs.CMDERR_NONE) { + abstractcs.cmderr = abstractcs.CMDERR_BUSY; + } + bool autoexec = false; switch (i) { case 0: autoexec = abstractcs.autoexec0; break; @@ -376,6 +380,10 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) unsigned i = address - DMI_DATA0; dmdata.write32(4 * i, value); + if (abstractcs.busy && abstractcs.cmderr == abstractcs.CMDERR_NONE) { + abstractcs.cmderr = abstractcs.CMDERR_BUSY; + } + bool autoexec = false; switch (i) { case 0: autoexec = abstractcs.autoexec0; break; |