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| author | Palmer Dabbelt <palmer@dabbelt.com> | 2017-04-19 16:59:10 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-04-26 09:14:27 -0700 |
| commit | fe678ee09925b90058ff80c037341b873e6da429 (patch) | |
| tree | 26b624b3b5e80d0b5a92e5c029d97fd14a42eff3 /riscv/debug_module.cc | |
| parent | a5e5bc65794e1ad2090201c31bdea3129ae347e4 (diff) | |
| download | spike-fe678ee09925b90058ff80c037341b873e6da429.zip spike-fe678ee09925b90058ff80c037341b873e6da429.tar.gz spike-fe678ee09925b90058ff80c037341b873e6da429.tar.bz2 | |
Have ndmreset reset the processor
Diffstat (limited to 'riscv/debug_module.cc')
| -rw-r--r-- | riscv/debug_module.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 533b959..5f66ebe 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -437,6 +437,9 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) debug_rom_flags[dmcontrol.hartsel] |= (1 << DEBUG_ROM_FLAG_RESUME); resumeack[dmcontrol.hartsel] = false; } + if (dmcontrol.ndmreset) { + proc->reset(); + } } } return true; |