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author | Tim Newsome <tim@sifive.com> | 2018-01-12 15:26:00 -0800 |
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committer | Tim Newsome <tim@sifive.com> | 2018-01-18 14:31:48 -0800 |
commit | cd1e73b4eda7ec555f2cb832fe98d618c377ea65 (patch) | |
tree | 2cb499ce9dbd46efd143774783723c2b26da6948 /riscv/debug_module.cc | |
parent | 11780eabc0147a58c575d089c4afe5732b55bb05 (diff) | |
download | spike-cd1e73b4eda7ec555f2cb832fe98d618c377ea65.zip spike-cd1e73b4eda7ec555f2cb832fe98d618c377ea65.tar.gz spike-cd1e73b4eda7ec555f2cb832fe98d618c377ea65.tar.bz2 |
Support debug system bus access.
Diffstat (limited to 'riscv/debug_module.cc')
-rw-r--r-- | riscv/debug_module.cc | 191 |
1 files changed, 177 insertions, 14 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 981e991..2bc480a 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -23,18 +23,6 @@ debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize) : debug_abstract_start(debug_progbuf_start - debug_abstract_size*4), sim(sim) { - dmcontrol = {0}; - - dmstatus = {0}; - dmstatus.impebreak = true; - dmstatus.authenticated = 1; - dmstatus.version = 2; - - abstractcs = {0}; - abstractcs.progbufsize = progbufsize; - - abstractauto = {0}; - program_buffer = new uint8_t[program_buffer_bytes]; memset(halted, 0, sizeof(halted)); @@ -51,6 +39,8 @@ debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize) : jal(ZERO, debug_abstract_start - DEBUG_ROM_WHERETO)); memset(debug_abstract, 0, sizeof(debug_abstract)); + + reset(); } debug_module_t::~debug_module_t() @@ -78,6 +68,14 @@ void debug_module_t::reset() abstractcs.progbufsize = progbufsize; abstractauto = {0}; + + sbcs = {0}; + sbcs.version = 1; + sbcs.access64 = true; + sbcs.access32 = true; + sbcs.access16 = true; + sbcs.access8 = true; + sbcs.asize = sizeof(reg_t) * 8; } void debug_module_t::add_device(bus_t *bus) { @@ -228,6 +226,87 @@ processor_t *debug_module_t::current_proc() const return proc; } +unsigned debug_module_t::sb_access_bits() +{ + return 8 << sbcs.sbaccess; +} + +void debug_module_t::sb_autoincrement() +{ + if (!sbcs.autoincrement) + return; + + uint64_t value = sbaddress[0] + sb_access_bits() / 8; + sbaddress[0] = value; + uint32_t carry = value >> 32; + + value = sbaddress[1] + carry; + sbaddress[1] = value; + carry = value >> 32; + + value = sbaddress[2] + carry; + sbaddress[2] = value; + carry = value >> 32; + + sbaddress[3] += carry; +} + +void debug_module_t::sb_read() +{ + reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0]; + D(fprintf(stderr, "sb_read() @ 0x%lx\n", address)); + try { + switch (sbcs.sbaccess) { + case 0: + sbdata[0] = sim->debug_mmu->load_uint8(address); + break; + case 1: + sbdata[0] = sim->debug_mmu->load_uint16(address); + break; + case 2: + sbdata[0] = sim->debug_mmu->load_uint32(address); + D(fprintf(stderr, " -> 0x%x\n", sbdata[0])); + break; + case 3: + { + uint64_t value = sim->debug_mmu->load_uint32(address); + sbdata[0] = value; + sbdata[1] = value >> 32; + break; + } + default: + sbcs.error = 3; + break; + } + } catch (trap_load_access_fault& t) { + sbcs.error = 2; + } +} + +void debug_module_t::sb_write() +{ + reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0]; + D(fprintf(stderr, "sb_write() 0x%x @ 0x%lx\n", sbdata[0], address)); + switch (sbcs.sbaccess) { + case 0: + sim->debug_mmu->store_uint8(address, sbdata[0]); + break; + case 1: + sim->debug_mmu->store_uint16(address, sbdata[0]); + break; + case 2: + sim->debug_mmu->store_uint32(address, sbdata[0]); + break; + case 3: + sim->debug_mmu->store_uint64(address, + (((uint64_t) sbdata[1]) << 32) | sbdata[0]); + break; + default: + sbcs.error = 3; + break; + } +} + bool debug_module_t::dmi_read(unsigned address, uint32_t *value) { uint32_t result = 0; @@ -343,6 +422,50 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) result = set_field(result, DMI_HARTINFO_DATASIZE, abstractcs.datacount); result = set_field(result, DMI_HARTINFO_DATAADDR, debug_data_start); break; + case DMI_SBCS: + result = set_field(result, DMI_SBCS_VERSION, sbcs.version); + result = set_field(result, DMI_SBCS_SBREADONADDR, sbcs.readonaddr); + result = set_field(result, DMI_SBCS_SBACCESS, sbcs.sbaccess); + result = set_field(result, DMI_SBCS_SBAUTOINCREMENT, sbcs.autoincrement); + result = set_field(result, DMI_SBCS_SBREADONDATA, sbcs.readondata); + result = set_field(result, DMI_SBCS_SBERROR, sbcs.error); + result = set_field(result, DMI_SBCS_SBASIZE, sbcs.asize); + result = set_field(result, DMI_SBCS_SBACCESS128, sbcs.access128); + result = set_field(result, DMI_SBCS_SBACCESS64, sbcs.access64); + result = set_field(result, DMI_SBCS_SBACCESS32, sbcs.access32); + result = set_field(result, DMI_SBCS_SBACCESS16, sbcs.access16); + result = set_field(result, DMI_SBCS_SBACCESS8, sbcs.access8); + break; + case DMI_SBADDRESS0: + result = sbaddress[0]; + break; + case DMI_SBADDRESS1: + result = sbaddress[1]; + break; + case DMI_SBADDRESS2: + result = sbaddress[2]; + break; + case DMI_SBADDRESS3: + result = sbaddress[3]; + break; + case DMI_SBDATA0: + result = sbdata[0]; + if (sbcs.error == 0) { + sb_autoincrement(); + if (sbcs.readondata) { + sb_read(); + } + } + break; + case DMI_SBDATA1: + result = sbdata[1]; + break; + case DMI_SBDATA2: + result = sbdata[2]; + break; + case DMI_SBDATA3: + result = sbdata[3]; + break; default: result = 0; D(fprintf(stderr, "Unexpected. Returning Error.")); @@ -462,6 +585,8 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) switch (address) { case DMI_DMCONTROL: { + if (!dmcontrol.dmactive && get_field(value, DMI_DMCONTROL_DMACTIVE)) + reset(); dmcontrol.dmactive = get_field(value, DMI_DMCONTROL_DMACTIVE); if (dmcontrol.dmactive) { dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ); @@ -469,8 +594,6 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) dmcontrol.hartreset = get_field(value, DMI_DMCONTROL_HARTRESET); dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET); dmcontrol.hartsel = get_field(value, DMI_DMCONTROL_HARTSEL); - } else { - reset(); } processor_t *proc = current_proc(); if (proc) { @@ -506,6 +629,46 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) abstractauto.autoexecdata = get_field(value, DMI_ABSTRACTAUTO_AUTOEXECDATA); return true; + case DMI_SBCS: + sbcs.readonaddr = get_field(value, DMI_SBCS_SBREADONADDR); + sbcs.sbaccess = get_field(value, DMI_SBCS_SBACCESS); + sbcs.autoincrement = get_field(value, DMI_SBCS_SBAUTOINCREMENT); + sbcs.readondata = get_field(value, DMI_SBCS_SBREADONDATA); + sbcs.error &= ~get_field(value, DMI_SBCS_SBERROR); + return true; + case DMI_SBADDRESS0: + sbaddress[0] = value; + if (sbcs.error == 0 && sbcs.readonaddr) { + sb_read(); + } + return true; + case DMI_SBADDRESS1: + sbaddress[1] = value; + return true; + case DMI_SBADDRESS2: + sbaddress[2] = value; + return true; + case DMI_SBADDRESS3: + sbaddress[3] = value; + return true; + case DMI_SBDATA0: + sbdata[0] = value; + if (sbcs.error == 0) { + sb_write(); + if (sbcs.autoincrement && sbcs.error == 0) { + sb_autoincrement(); + } + } + return true; + case DMI_SBDATA1: + sbdata[1] = value; + return true; + case DMI_SBDATA2: + sbdata[2] = value; + return true; + case DMI_SBDATA3: + sbdata[3] = value; + return true; } } return false; |