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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-08 21:45:32 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-09 18:33:53 -0700 |
| commit | b6f7b65b659d485990430e5db3b7dc4a6ee94f8f (patch) | |
| tree | 1f7dd2d4be62c13ad0d726f7e9ce0abe5d0a5f6b /riscv/debug_module.cc | |
| parent | 942662a2334da7a6cb2f5015fd2145f578b2df76 (diff) | |
| download | spike-b6f7b65b659d485990430e5db3b7dc4a6ee94f8f.zip spike-b6f7b65b659d485990430e5db3b7dc4a6ee94f8f.tar.gz spike-b6f7b65b659d485990430e5db3b7dc4a6ee94f8f.tar.bz2 | |
op: update CSR
1. add new hypervisor csr
2. add debug module csr
3. add some new high part register for rv32
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/debug_module.cc')
| -rw-r--r-- | riscv/debug_module.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 5c7d2f1..8ace1b9 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -590,10 +590,10 @@ bool debug_module_t::perform_abstract_command() if (is_fpu_reg(regno)) { // Save S0 - write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH)); + write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH0)); // Save mstatus write32(debug_abstract, i++, csrr(S0, CSR_MSTATUS)); - write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH + 1)); + write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH1)); // Set mstatus.fs assert((MSTATUS_FS & 0xfff) == 0); write32(debug_abstract, i++, lui(S0, MSTATUS_FS >> 12)); @@ -602,7 +602,7 @@ bool debug_module_t::perform_abstract_command() if (regno < 0x1000 && config.support_abstract_csr_access) { if (!is_fpu_reg(regno)) { - write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH)); + write32(debug_abstract, i++, csrw(S0, CSR_DSCRATCH0)); } if (write) { @@ -634,7 +634,7 @@ bool debug_module_t::perform_abstract_command() } } if (!is_fpu_reg(regno)) { - write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH)); + write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH0)); } } else if (regno >= 0x1000 && regno < 0x1020) { @@ -709,10 +709,10 @@ bool debug_module_t::perform_abstract_command() if (is_fpu_reg(regno)) { // restore mstatus - write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH + 1)); + write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH1)); write32(debug_abstract, i++, csrw(S0, CSR_MSTATUS)); // restore s0 - write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH)); + write32(debug_abstract, i++, csrr(S0, CSR_DSCRATCH0)); } } |