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authorAndrew Waterman <andrew@sifive.com>2020-02-21 12:12:57 -0800
committerAndrew Waterman <andrew@sifive.com>2020-02-21 12:12:57 -0800
commitb1563b8af6bd44cf8dd2190c7695b8fe4310c268 (patch)
tree82cc197bfb7b5ae80f8a3a944f4764ff1bc65293 /riscv/debug_module.cc
parent1ef875316adee8174fe2cf83317f59019d3c1aa2 (diff)
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Initialize some uninitialized state
Diffstat (limited to 'riscv/debug_module.cc')
-rw-r--r--riscv/debug_module.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index f5d33f2..499f552 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -43,7 +43,8 @@ debug_module_t::debug_module_t(sim_t *sim, const debug_module_config_t &config)
// The spec lets a debugger select nonexistent harts. Create hart_state for
// them because I'm too lazy to add the code to just ignore accesses.
hart_state(1 << field_width(sim->nprocs())),
- hart_array_mask(sim->nprocs())
+ hart_array_mask(sim->nprocs()),
+ rti_remaining(0)
{
D(fprintf(stderr, "debug_data_start=0x%x\n", debug_data_start));
D(fprintf(stderr, "debug_progbuf_start=0x%x\n", debug_progbuf_start));