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authorTim Newsome <tim@sifive.com>2018-02-27 12:30:46 -0800
committerTim Newsome <tim@sifive.com>2018-02-27 12:30:46 -0800
commitaa8cbb1ccd3856fd5e0437b0e24cfd7a3b794b8e (patch)
tree5ce67dd1233646c36bd8b5c0189618f4be1d767c /riscv/debug_module.cc
parent0329b0741a698f102d64be4f0538427978bacb83 (diff)
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Add debug module authentication.
Off by default, enabled with --debug-auth. The protocol is very simple (definitely not secure) to allow debuggers to test their authentication feature. To authenticate a debugger must: 1. Read authdata 2. Write to authdata the value that it just read, plus 1
Diffstat (limited to 'riscv/debug_module.cc')
-rw-r--r--riscv/debug_module.cc30
1 files changed, 28 insertions, 2 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 12956a5..f10c866 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -16,10 +16,12 @@
///////////////////////// debug_module_t
-debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits) :
+debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits,
+ bool require_authentication) :
progbufsize(progbufsize),
program_buffer_bytes(4 + 4*progbufsize),
max_bus_master_bits(max_bus_master_bits),
+ require_authentication(require_authentication),
debug_progbuf_start(debug_data_start - program_buffer_bytes),
debug_abstract_start(debug_progbuf_start - debug_abstract_size*4),
sim(sim)
@@ -61,7 +63,7 @@ void debug_module_t::reset()
dmstatus = {0};
dmstatus.impebreak = true;
- dmstatus.authenticated = 1;
+ dmstatus.authenticated = !require_authentication;
dmstatus.version = 2;
abstractcs = {0};
@@ -83,6 +85,8 @@ void debug_module_t::reset()
sbcs.access16 = true;
if (max_bus_master_bits >= 8)
sbcs.access8 = true;
+
+ challenge = random();
}
void debug_module_t::add_device(bus_t *bus) {
@@ -458,6 +462,9 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
case DMI_SBDATA3:
result = sbdata[3];
break;
+ case DMI_AUTHDATA:
+ result = challenge;
+ break;
default:
result = 0;
D(fprintf(stderr, "Unexpected. Returning Error."));
@@ -548,6 +555,11 @@ bool debug_module_t::perform_abstract_command()
bool debug_module_t::dmi_write(unsigned address, uint32_t value)
{
D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value));
+
+ if (!dmstatus.authenticated && address != DMI_AUTHDATA &&
+ address != DMI_DMCONTROL)
+ return false;
+
if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) {
unsigned i = address - DMI_DATA0;
if (!abstractcs.busy)
@@ -580,6 +592,8 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value)
if (!dmcontrol.dmactive && get_field(value, DMI_DMCONTROL_DMACTIVE))
reset();
dmcontrol.dmactive = get_field(value, DMI_DMCONTROL_DMACTIVE);
+ if (!dmstatus.authenticated)
+ return true;
if (dmcontrol.dmactive) {
dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ);
dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ);
@@ -662,6 +676,18 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value)
case DMI_SBDATA3:
sbdata[3] = value;
return true;
+ case DMI_AUTHDATA:
+ D(fprintf(stderr, "debug authentication: got 0x%x; 0x%x unlocks\n", value,
+ challenge + secret));
+ if (require_authentication) {
+ if (value == challenge + secret) {
+ dmstatus.authenticated = true;
+ } else {
+ dmstatus.authenticated = false;
+ challenge = random();
+ }
+ }
+ return true;
}
}
return false;