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author | Tim Newsome <tim@sifive.com> | 2018-03-07 17:17:39 -0800 |
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committer | GitHub <noreply@github.com> | 2018-03-07 17:17:39 -0800 |
commit | 9d1e10a36e771bf8cfbf515e07e856e021c1007a (patch) | |
tree | 949d7e13d9d2491381e510369c6ddd376e9ee739 /riscv/debug_module.cc | |
parent | 4a97a05a6e806f7abcb6cd30685093aa5b9331a9 (diff) | |
parent | aa8cbb1ccd3856fd5e0437b0e24cfd7a3b794b8e (diff) | |
download | spike-9d1e10a36e771bf8cfbf515e07e856e021c1007a.zip spike-9d1e10a36e771bf8cfbf515e07e856e021c1007a.tar.gz spike-9d1e10a36e771bf8cfbf515e07e856e021c1007a.tar.bz2 |
Merge pull request #177 from riscv/debug_auth
Add debug module authentication.
Diffstat (limited to 'riscv/debug_module.cc')
-rw-r--r-- | riscv/debug_module.cc | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index de54a83..74c3023 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -16,10 +16,12 @@ ///////////////////////// debug_module_t -debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits) : +debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits, + bool require_authentication) : progbufsize(progbufsize), program_buffer_bytes(4 + 4*progbufsize), max_bus_master_bits(max_bus_master_bits), + require_authentication(require_authentication), debug_progbuf_start(debug_data_start - program_buffer_bytes), debug_abstract_start(debug_progbuf_start - debug_abstract_size*4), sim(sim) @@ -65,7 +67,7 @@ void debug_module_t::reset() dmstatus = {0}; dmstatus.impebreak = true; - dmstatus.authenticated = 1; + dmstatus.authenticated = !require_authentication; dmstatus.version = 2; abstractcs = {0}; @@ -87,6 +89,8 @@ void debug_module_t::reset() sbcs.access16 = true; if (max_bus_master_bits >= 8) sbcs.access8 = true; + + challenge = random(); } void debug_module_t::add_device(bus_t *bus) { @@ -462,6 +466,9 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) case DMI_SBDATA3: result = sbdata[3]; break; + case DMI_AUTHDATA: + result = challenge; + break; default: result = 0; D(fprintf(stderr, "Unexpected. Returning Error.")); @@ -611,6 +618,11 @@ bool debug_module_t::perform_abstract_command() bool debug_module_t::dmi_write(unsigned address, uint32_t value) { D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value)); + + if (!dmstatus.authenticated && address != DMI_AUTHDATA && + address != DMI_DMCONTROL) + return false; + if (address >= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) { unsigned i = address - DMI_DATA0; if (!abstractcs.busy) @@ -643,6 +655,8 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) if (!dmcontrol.dmactive && get_field(value, DMI_DMCONTROL_DMACTIVE)) reset(); dmcontrol.dmactive = get_field(value, DMI_DMCONTROL_DMACTIVE); + if (!dmstatus.authenticated) + return true; if (dmcontrol.dmactive) { dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ); dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ); @@ -725,6 +739,18 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) case DMI_SBDATA3: sbdata[3] = value; return true; + case DMI_AUTHDATA: + D(fprintf(stderr, "debug authentication: got 0x%x; 0x%x unlocks\n", value, + challenge + secret)); + if (require_authentication) { + if (value == challenge + secret) { + dmstatus.authenticated = true; + } else { + dmstatus.authenticated = false; + challenge = random(); + } + } + return true; } } return false; |