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| author | Tim Newsome <tim@sifive.com> | 2018-09-05 13:27:58 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2018-09-05 13:29:22 -0700 |
| commit | 7de234911f6eb57fccf9609734ba807fa8f14cba (patch) | |
| tree | 3e1ea10f2ff870cca7d04f62a1c79790d52781c2 /riscv/debug_module.cc | |
| parent | aff796dbf6db66a2df53b0ca270382f0ce02da74 (diff) | |
| download | spike-7de234911f6eb57fccf9609734ba807fa8f14cba.zip spike-7de234911f6eb57fccf9609734ba807fa8f14cba.tar.gz spike-7de234911f6eb57fccf9609734ba807fa8f14cba.tar.bz2 | |
Fix cut-and-paste bug in 64-bit SBA loads.
Fixes #234.
Diffstat (limited to 'riscv/debug_module.cc')
| -rw-r--r-- | riscv/debug_module.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index b209347..96de3c8 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -280,7 +280,7 @@ void debug_module_t::sb_read() } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) { sbdata[0] = sim->debug_mmu->load_uint32(address); } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) { - uint64_t value = sim->debug_mmu->load_uint32(address); + uint64_t value = sim->debug_mmu->load_uint64(address); sbdata[0] = value; sbdata[1] = value >> 32; } else { |