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| author | Stefan O'Rear <stefanor@cox.net> | 2016-12-16 18:24:41 -0800 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2016-12-16 20:30:24 -0800 |
| commit | 07ff3f3b0ba7d67e13f686da501bbbffca8589c8 (patch) | |
| tree | 54c34f988d9d9f982ffe0024a0173736fdcf649e /riscv/debug_module.cc | |
| parent | 7e31f495358df52e49b9a5fec7ce273d706b1300 (diff) | |
| download | spike-07ff3f3b0ba7d67e13f686da501bbbffca8589c8.zip spike-07ff3f3b0ba7d67e13f686da501bbbffca8589c8.tar.gz spike-07ff3f3b0ba7d67e13f686da501bbbffca8589c8.tar.bz2 | |
Use correct format codes for reg_t and size_t
Fixes 32-bit build.
Diffstat (limited to 'riscv/debug_module.cc')
| -rw-r--r-- | riscv/debug_module.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 17b8b45..8bcc60e 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -19,7 +19,7 @@ bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes) return true; } - fprintf(stderr, "ERROR: invalid load from debug module: %ld bytes at 0x%016" + fprintf(stderr, "ERROR: invalid load from debug module: %zd bytes at 0x%016" PRIx64 "\n", len, addr); return false; } @@ -29,7 +29,7 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes) addr = DEBUG_START + addr; if (addr & (len-1)) { - fprintf(stderr, "ERROR: unaligned store to debug module: %ld bytes at 0x%016" + fprintf(stderr, "ERROR: unaligned store to debug module: %zd bytes at 0x%016" PRIx64 "\n", len, addr); return false; } @@ -47,7 +47,7 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes) return true; } - fprintf(stderr, "ERROR: invalid store to debug module: %ld bytes at 0x%016" + fprintf(stderr, "ERROR: invalid store to debug module: %zd bytes at 0x%016" PRIx64 "\n", len, addr); return false; } |