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author | Tim Newsome <tim@sifive.com> | 2016-05-01 12:05:48 -0700 |
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committer | Tim Newsome <tim@sifive.com> | 2016-05-23 12:12:11 -0700 |
commit | 990c6c48098e83584edf5282d119187abae04a4d (patch) | |
tree | d2ba581b281dce0c329822f98cc7c21faf868323 /riscv/debug_module.cc | |
parent | 57ff1b6595e485b8b002238ddbd10483bbd62fb3 (diff) | |
download | spike-990c6c48098e83584edf5282d119187abae04a4d.zip spike-990c6c48098e83584edf5282d119187abae04a4d.tar.gz spike-990c6c48098e83584edf5282d119187abae04a4d.tar.bz2 |
Have Debug memory kind of working again.
Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
Diffstat (limited to 'riscv/debug_module.cc')
-rw-r--r-- | riscv/debug_module.cc | 35 |
1 files changed, 9 insertions, 26 deletions
diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 2cda772..e3eb16b 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -5,19 +5,17 @@ #include "debug_rom/debug_rom.h" -debug_module_t::debug_module_t() -{ - /* Copy Debug ROM into the page. */ - memcpy(raw_page + DEBUG_ROM_START - DEBUG_START, - debug_rom_raw, debug_rom_raw_len); -} - bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes) { addr = DEBUG_START + addr; if (addr >= DEBUG_RAM_START && addr + len <= DEBUG_RAM_END) { - memcpy(bytes, raw_page + addr - DEBUG_START, len); + memcpy(bytes, debug_ram + addr - DEBUG_RAM_START, len); + return true; + } + + if (addr >= DEBUG_ROM_START && addr + len <= DEBUG_ROM_END) { + memcpy(bytes, debug_rom_raw + addr - DEBUG_ROM_START, len); return true; } @@ -37,7 +35,7 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes) } if (addr >= DEBUG_RAM_START && addr + len <= DEBUG_RAM_END) { - memcpy(raw_page + addr - DEBUG_START, bytes, len); + memcpy(debug_ram + addr - DEBUG_RAM_START, bytes, len); return true; } else if (len == 4 && addr == DEBUG_CLEARDEBINT) { clear_interrupt(bytes[0] | (bytes[1] << 8) | @@ -52,7 +50,7 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes) void debug_module_t::ram_write32(unsigned int index, uint32_t value) { - char* base = raw_page + DEBUG_RAM_START - DEBUG_START + index * 4; + char* base = debug_ram + index * 4; base[0] = value & 0xff; base[1] = (value >> 8) & 0xff; base[2] = (value >> 16) & 0xff; @@ -63,25 +61,10 @@ uint32_t debug_module_t::ram_read32(unsigned int index) { // It'd be better for raw_page (and all memory) to be unsigned chars, but mem // in sim_t is just chars, so I'm following that convention. - unsigned char* base = (unsigned char*) - (raw_page + DEBUG_RAM_START - DEBUG_START + index * 4); + unsigned char* base = (unsigned char*) (debug_ram + index * 4); uint32_t value = ((uint32_t) base[0]) | (((uint32_t) base[1]) << 8) | (((uint32_t) base[2]) << 16) | (((uint32_t) base[3]) << 24); return value; } - -char* debug_module_t::page(reg_t paddr) -{ - fprintf(stderr, "dm::page(0x%lx)\n", paddr); - - assert(PGSHIFT == 12); - - if (paddr == (DEBUG_START & PGMASK)) { - return raw_page; - } - - fprintf(stderr, "ERROR: invalid page to debug module at 0x%lx\n", paddr); - return NULL; -} |