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authorTim Newsome <tim@sifive.com>2018-01-12 15:26:00 -0800
committerTim Newsome <tim@sifive.com>2018-01-18 14:31:48 -0800
commitcd1e73b4eda7ec555f2cb832fe98d618c377ea65 (patch)
tree2cb499ce9dbd46efd143774783723c2b26da6948 /riscv/debug_defines.h
parent11780eabc0147a58c575d089c4afe5732b55bb05 (diff)
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Support debug system bus access.
Diffstat (limited to 'riscv/debug_defines.h')
-rw-r--r--riscv/debug_defines.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/riscv/debug_defines.h b/riscv/debug_defines.h
index 58826f0..0d843b0 100644
--- a/riscv/debug_defines.h
+++ b/riscv/debug_defines.h
@@ -1041,8 +1041,27 @@
#define DMI_AUTHDATA_DATA_OFFSET 0
#define DMI_AUTHDATA_DATA_LENGTH 32
#define DMI_AUTHDATA_DATA (0xffffffffU << DMI_AUTHDATA_DATA_OFFSET)
+#define DMI_SBADDRESS3 0x37
+/*
+* Accesses bits 127:96 of the physical address in {\tt sbaddress} (if
+* the system address bus is that wide).
+ */
+#define DMI_SBADDRESS3_ADDRESS_OFFSET 0
+#define DMI_SBADDRESS3_ADDRESS_LENGTH 32
+#define DMI_SBADDRESS3_ADDRESS (0xffffffffU << DMI_SBADDRESS3_ADDRESS_OFFSET)
#define DMI_SBCS 0x38
/*
+* 0: The System Bus interface conforms to mainline drafts of this
+* spec older than 1 January, 2018.
+*
+* 1: The System Bus interface conforms to this version of the spec.
+*
+* Other values are reserved for future versions.
+ */
+#define DMI_SBCS_VERSION_OFFSET 29
+#define DMI_SBCS_VERSION_LENGTH 3
+#define DMI_SBCS_VERSION (0x7U << DMI_SBCS_VERSION_OFFSET)
+/*
* When a 1, every write to \Rsbaddresszero automatically triggers a
* system bus read at the new address.
*/