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| author | Tim Newsome <tim@sifive.com> | 2022-03-15 10:58:04 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-03-30 10:41:45 -0700 |
| commit | fd315a0ddebdfbee71edbfb60680cdbf43bc4c38 (patch) | |
| tree | ba4fe724efe3fc8da17b1012b825a2d77f0ba91f /riscv/csrs.h | |
| parent | 16ed520e8d35a0eaa56b708aa540400312acdc09 (diff) | |
| download | spike-fd315a0ddebdfbee71edbfb60680cdbf43bc4c38.zip spike-fd315a0ddebdfbee71edbfb60680cdbf43bc4c38.tar.gz spike-fd315a0ddebdfbee71edbfb60680cdbf43bc4c38.tar.bz2 | |
Move tdata2 into mcontrol_t
Diffstat (limited to 'riscv/csrs.h')
| -rw-r--r-- | riscv/csrs.h | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/riscv/csrs.h b/riscv/csrs.h index 0cbe8c5..c83283e 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -574,13 +574,10 @@ class tdata1_csr_t: public csr_t { class tdata2_csr_t: public csr_t { public: - tdata2_csr_t(processor_t* const proc, const reg_t addr, const size_t count); + tdata2_csr_t(processor_t* const proc, const reg_t addr); virtual reg_t read() const noexcept override; - reg_t read(const size_t idx) const noexcept; protected: virtual bool unlogged_write(const reg_t val) noexcept override; - private: - std::vector<reg_t> vals; }; // For CSRs that are only writable from debug mode |