Mask hideleg by mideleg

According to spec clarification:
https://github.com/riscv/riscv-isa-manual/pull/771

This has no functional effect today, because all the active bits of
hideleg are tied to 1 inside mideleg.

1 files changed, 9 insertions, 0 deletions

diff --git a/riscv/csrs.h b/riscv/csrs.h
index cf63d4d..6e218db 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -511,6 +511,15 @@ class hypervisor_csr_t: public basic_csr_t {
 };
 
 
+class hideleg_csr_t: public masked_csr_t {
+ public:
+  hideleg_csr_t(processor_t* const proc, const reg_t addr, csr_t_p mideleg);
+  virtual reg_t read() const noexcept override;
+ private:
+  csr_t_p mideleg;
+};
+
+
 class hgatp_csr_t: public basic_csr_t {
  public:
   hgatp_csr_t(processor_t* const proc, const reg_t addr);