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authorsoberl@nvidia.com <soberl@nvidia.com>2022-05-03 19:38:07 -0700
committersoberl@nvidia.com <soberl@nvidia.com>2022-05-04 18:26:24 -0700
commit84a98f6f718cd482710238042eac3d2b855c6768 (patch)
tree31e3e1e5cb9a7459e3678b75df953390cdfb025d /riscv/csrs.h
parent1df65613df9970dc7f5c2f3d1bf343dbb0497828 (diff)
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Implement the new csr mseccfg for ePMP as dummy
Diffstat (limited to 'riscv/csrs.h')
-rw-r--r--riscv/csrs.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/riscv/csrs.h b/riscv/csrs.h
index fb27ae6..660ddd1 100644
--- a/riscv/csrs.h
+++ b/riscv/csrs.h
@@ -89,6 +89,11 @@ class pmpaddr_csr_t: public csr_t {
// Is the specified access allowed given the pmpcfg privileges?
bool access_ok(access_type type, reg_t mode) const noexcept;
+ // To check lock bit status from outside like mseccfg
+ bool is_locked() const noexcept {
+ return cfg & PMP_L;
+ }
+
protected:
virtual bool unlogged_write(const reg_t val) noexcept override;
private:
@@ -122,6 +127,17 @@ class pmpcfg_csr_t: public csr_t {
virtual bool unlogged_write(const reg_t val) noexcept override;
};
+class mseccfg_csr_t: public basic_csr_t {
+ public:
+ mseccfg_csr_t(processor_t* const proc, const reg_t addr);
+ bool get_mml() const noexcept;
+ bool get_mmwp() const noexcept;
+ bool get_rlb() const noexcept;
+ protected:
+ virtual bool unlogged_write(const reg_t val) noexcept override;
+};
+
+typedef std::shared_ptr<mseccfg_csr_t> mseccfg_csr_t_p;
// For CSRs that have a virtualized copy under another name. Each
// instance of virtualized_csr_t will read/write one of two CSRs,