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| author | Andrew Waterman <andrew@sifive.com> | 2022-03-15 23:01:45 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-03-16 13:47:27 -0700 |
| commit | 5698007158cc5f0d9b39c7a5446ddb7cbc935b2b (patch) | |
| tree | 28092599053350f3106667aa4f3eeccc1455db6f /riscv/csrs.h | |
| parent | a522178805264c9bfb8ebd68db33fabfa9ddd3ae (diff) | |
| download | spike-5698007158cc5f0d9b39c7a5446ddb7cbc935b2b.zip spike-5698007158cc5f0d9b39c7a5446ddb7cbc935b2b.tar.gz spike-5698007158cc5f0d9b39c7a5446ddb7cbc935b2b.tar.bz2 | |
Inline most implicit accesses to fflags/frm
Diffstat (limited to 'riscv/csrs.h')
| -rw-r--r-- | riscv/csrs.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/riscv/csrs.h b/riscv/csrs.h index 946d06c..0cbe8c5 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -621,7 +621,7 @@ class dcsr_csr_t: public csr_t { typedef std::shared_ptr<dcsr_csr_t> dcsr_csr_t_p; -class float_csr_t: public masked_csr_t { +class float_csr_t final: public masked_csr_t { public: float_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask, const reg_t init); virtual void verify_permissions(insn_t insn, bool write) const override; @@ -629,6 +629,8 @@ class float_csr_t: public masked_csr_t { virtual bool unlogged_write(const reg_t val) noexcept override; }; +typedef std::shared_ptr<float_csr_t> float_csr_t_p; + // For a CSR like FCSR, that is actually a view into multiple // underlying registers. |