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author | Scott Johnson <scott.johnson@arilinc.com> | 2021-10-06 11:09:35 -0700 |
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committer | Scott Johnson <scott.johnson@arilinc.com> | 2021-10-06 11:09:35 -0700 |
commit | 4c185074899b6a57db8d45a162faa0a881451f7b (patch) | |
tree | 90f3e9e877ac0d2a809c8ca7a9daa7c853419213 /riscv/csrs.h | |
parent | 4618ca82bea2794dacc8d94ad93561fd94612e1b (diff) | |
download | spike-4c185074899b6a57db8d45a162faa0a881451f7b.zip spike-4c185074899b6a57db8d45a162faa0a881451f7b.tar.gz spike-4c185074899b6a57db8d45a162faa0a881451f7b.tar.bz2 |
Let each sstatus CSR determine extension enable
No functional change intended.
This will allow me to consider whether the given field exists at all,
which I will eventually use to fix #823.
Diffstat (limited to 'riscv/csrs.h')
-rw-r--r-- | riscv/csrs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/csrs.h b/riscv/csrs.h index 3eb6bf5..bb53876 100644 --- a/riscv/csrs.h +++ b/riscv/csrs.h @@ -180,6 +180,8 @@ class cause_csr_t: public basic_csr_t { class base_status_csr_t: public csr_t { public: base_status_csr_t(processor_t* const proc, const reg_t addr); + // Return true if the specified bits are not 00 (Off) + bool enabled(const reg_t which); protected: reg_t adjust_sd(const reg_t val) const noexcept; void maybe_flush_tlb(const reg_t newval) noexcept; |